Figure 48.
MMU Pre-Fetch Register (PREFETCH_REG)
DSP Side
16
Reserved
MPU Side
31
Reserved
R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
Note:
Table 22. MMU Pre-Fetch Register (PREFETCH_REG) Field Descriptions
Bits
Field
31−14 Reserved
13−0
PREFETCH_ADDR
6.5.3
MMU Pre-Fetch Status Register (WALKING_ST_REG)
Figure 49.
MMU Pre-Fetch Status Register (WALKING_ST_REG)
31
Note:
R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
SPRU890A
14
R-0
14
R-0
Value Description
These bits are not used.
Virtual address tag of the TLB entry to be pre-fetched.
Use the WALKING_ST_REG to determine when the table walking logic has
completed a TLB-entry pre-fetch operation. This register can also be used to
determine when the table walking logic is busy handling a miss in the TLB.
Reserved
R-0
DSP Memory Management Unit
13
PREFETCH_ADDR
W-0
13
PREFETCH_ADDR
R-0
2
WORKING
DSP Subsystem
0
0
1
0
WALK_
PREFETCH_
ON
R-0
R-0
103