Page 1 OMAP5910/5912 Multimedia Processor DSP Subsystem Reference Guide Literature Number: SPRU890A May 2005...
Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
Page 3 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments Documentation that describes the OMAP5910/5912 devices, related peripherals, and other technical collateral, is available in the OMAP5910 Product Folder on TI’s website: www.ti.com/omap5910, and in the OMAP5912 Product Folder on TI’s website: www.ti.com/omap5912.
Page 4 DSP Subsystem SPRU890A...
Page 5: Table Of Contents
..............Differences Between the OMAP5910 and OMAP5912 DSP Subsystems .
Page 6 Contents Configuring the I-Cache With the 2-Way Cache and One RAM Set ....4.4.1 Architectural/Operational Description ........4.4.2 Software Configuration .
Page 7 Contents MMU Architecture ............6.2.1 Summary of Address Translation Process .
Page 8 Contents DSP DMA ............... Overview .
Page 9 ............11.2.1 OMAP5910 First Level Interrupt Mapping and Interrupt Registers .
Page 10 Contents 12 DSP Subsystem Reset, Clocking, Idle Control, and Boot ......12.1 Reset Control .
Page 11 Figures OMAP5910 DSP Subsystem and Modules ........
Page 12 Figures First-Level Descriptor Address Calculation ........First-Level Descriptor Format Based on Two Least-Significant Bits .
Page 13 ......... . IFR0 and IER0 Bit Locations (OMAP5910) .
Page 14 Tables Tables OMAP5910/5912 DSP Subsystem Global Memory Map ......Fetch Address Field Descriptions for the 2-Way Cache Register Field Descriptions .
Page 15 ........... . DSP DMA Controller Synchronization Events for OMAP5910 .
Page 16 ......Peripherals Affected by Access Factor Bits (OMAP5910) ......
Page 17: Digital Signal Processor Subsystem Overview
The MPU core via the microprocessor unit interface (MPUI) Various standard memories via the external memory interface (EMIF) Various system peripherals via two TI peripheral bus (TIPB) bridges Figure 1 and Figure 2 in section 1.4 show block diagrams for the OMAP5910 and OMAP5912 DSP subsystems. Features...
Page 18 Digital Signal Processor Subsystem Overview DSP subsystem interfaces: External memory interface (EMIF) that connects the DSP core to external and loosely coupled memories MPUI port that permits access to DSP resources by the MPU and system DMA TIPB that provides two external bus interfaces for private and public peripherals DSP subsystem peripherals: Private peripherals are on the DSP private peripheral bus, and can...
Page 19: Differences Between The Omap5910 And Omap5912 Dsp Subsystems
The OMAP5910 and OMAP5912 DSP subsystems are very similar. The difference between the subsystems lies in the mix of the MPU/DSP shared peripherals. Functional Block Diagrams Figure 1 and Figure 2 show functional block diagrams of the OMAP5910 and OMAP5912 DSP subsystems. Figure 1. OMAP5910 DSP Subsystem and Modules...
Page 20: Omap5912 Dsp Subsystem And Modules
Digital Signal Processor Subsystem Overview Figure 2. OMAP5912 DSP Subsystem and Modules DSP Subsystem and Interfaces DSP private MPU/DSP shared DSP Module peripherals peripherals Endianess EMIF Mailbox conversion Internal memory buses Timers MPU/DSP static TMS320C55x shared DSP core 8xGPTIMERS I-Cache Watchdog timer UART1,2,3...
Page 21: C55X Dsp Core Overview
C55x DSP Core Overview C55x DSP Core Overview The DSP subsystem is based on the TMS320C55x DSP generation processor core. This section is intended to give a mere overview of the C55x DSP core. For detailed information, see the TMS320C55x DSP CPU Reference Guide (SPRU371).
Page 22: Introduction To The Dsp Core
C55x DSP Core Overview Introduction to the DSP Core The DSP core supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA controller activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle.
Page 23: Dsp Core Diagram
C55x DSP Core Overview Figure 3. DSP Core Diagram Data-read data buses BB, CB, DB (each 16 bits) Data-read address buses BAB, CAB, DAB (each 23 bits) Program-read data bus PB (32 bits) Program-read address bus PAB (24 bits) External data buses Memory Instruction...
Page 24: Introduction To The Hardware Accelerators
DSP core were operating alone. The hardware accelerators are utilized via functions from the TMS320C55x Image/Video Processing Library available from Texas Instruments. The Image/Video Processing Library implements many useful functions utilizing the hardware accelerators, including:...
Page 25 C55x DSP Core Overview There are three hardware accelerators included along with the C55x DSP core: DCT/IDCT Accelerator: This hardware accelerator implements Forward and Inverse DCT algorithms. These DCT/IDCT algorithms can enable a wide range of video compression standards including JPEG Encode/Decode, MPEG Video...
Page 26: Dsp Subsystem Memory
DSP Subsystem Memory DSP Subsystem Memory The DSP subsystem requires access to three different types of memory: program memory, data memory, and I/O memory. The DSP subsystem architecture uses a unified program and data memory space composed of memory internal and external to the DSP subsystem. Internal memory is made up of tightly coupled memory blocks, whereas DSP external memory is mapped to OMAP system memory.
Page 27: Internal Memory Connections In The Dsp Subsystem
DSP Subsystem Memory Configurable I-Cache structure The DSP instruction cache (I-Cache) module is a special-purpose, tightly coupled, RAM-based program memory. The module is designed to significantly improve DSP core performance by buffering the instructions most recently fetched from DSP external memory. The entire external program memory space is cacheable.
Page 28: Dsp External Memory Space
DSP Subsystem Memory DSP External Memory Space The DSP core and DMA controller use the external memory interface (EMIF) to access the DSP external memory. External memory for the DSP subsystem ranges from byte address 0x02 8000 to 0xFF 8000 if the internal PDROM is enabled, or to 0xFF FFFF if the PDROM is not enabled.
Page 29: Memory Maps
DSP core data accesses utilize 16-bit word addresses, while DSP core program fetches utilize byte addressing. DSP DMA data fetches always use byte addresses. Table 1. OMAP5910/5912 DSP Subsystem Global Memory Map Byte Address Range Word Address Range Internal Memory...
Page 30: Instruction Cache
Instruction Cache Instruction Cache Introduction On the OMAP5912/10 applications processors, instructions for the C55x DSP core can reside in internal memory or in DSP external memory. When instructions reside in DSP external memory, the instruction cache (I-Cache) can improve the overall system performance by buffering the most recent instructions accessed by the DSP core.
Page 31: Supported Cache Configurations
Instruction Cache Figure 5. Conceptual Block Diagram of the I-Cache in the DSP Subsystem OMAP device DSP subsystem DSP core I-Cache Cache control bits in Control logic ST3_55 to enable, freeze, and flush I-Cache Data read/write logic I-Cache registers to configure and monitor I-Cache Instruction storage memory banks...
Page 32: Instruction Cache Architecture
Instruction Cache Instruction Cache Architecture 4.2.1 Introduction to the I-Cache When the DSP core requests instructions, it requests 32 bits at a time. To initiate an instruction fetch, the DSP core sends a fetch request and a fetch address to the I-Cache. If the I-Cache is enabled, it handles the fetch request as follows.
Page 33: Instruction Cache Blocks
Instruction Cache Tag array. Each line has a tag field. When the I-Cache receives a 24-bit fetch address from the DSP core, the I-Cache interprets bits 23-13 as a tag. When a line gets filled, the associated tag is stored in the tag field for that line.
Page 34: Ram Sets 1 And 2
Instruction Cache Tag field. The RAM set has one 12-bit tag field that indicates which range of DSP external memory addresses are mapped to the RAM set. To select a tag for RAM set n (1 or 2), write to RAM set tag register n. When you write to the tag register, the I-Cache immediately fills the RAM set with all the 32-bit words in the address range specified by the tag.
Page 35: Instruction Cache Operation
Instruction Cache Address Type Pseudo Instruction Ext Memory DSP code Ext Memory GCR = #0xce2f ; Select 2−way cache and two RAM sets Ext Memory NWCR = #0x000f ; Initialize logic for 2−way cache Ext Memory RCR1 = #0x000f ; Initialize logic for RAM set 1 Ext Memory RCR2 = #0x000f ;...
Page 36: Fetch Address Fields For The 2-Way Cache Register
Instruction Cache Figure 8. Fetch Address Fields for the 2-Way Cache Register Index Offset Byte 11 bits 9 bits 2 bits 2 bits Note: R = Read, W = Write Table 2. Fetch Address Field Descriptions for the 2-Way Cache Register Field Descriptions Bits Field...
Page 37: Instruction Presence Check And I-Cache Response
Instruction Cache 4.2.3.2 Instruction Presence Check and Corresponding I-Cache Response When a fetch request arrives, the I-Cache performs an instruction presence check to determine whether the 32-bit requested word is available in the I-Cache. During the instruction presence check, the I-Cache performs two operations on both the 2-way cache and the RAM sets: 1) Compares the tag portion of the fetch address with the tag in the data array at the location referenced by the Index portion of the fetch address.
Page 38 Instruction Cache 4.2.3.3 Line Load Process When an instruction presence check results in a fetch from the DSP external memory, the 4-word DSP external memory block that contains the requested word is fetched and loaded into a line in the I-Cache. Figure 10 illustrates this line load process.
Page 39: Dsp Core Bits For Controlling The I-Cache
Instruction Cache Figure 10. Flow Chart of the Line Load Process I-Cache must load 2-way cache line or RAM set line Command EMIF to read four 32-bit words from DSP external memory word received Wait for next word Write word to line it the Line requested...
Page 40: Cafrz, Caen, And Caclr Bits In St3_55
RW-0 RW-0 RW-0 RW-0 RW-0 † This bit is not used in OMAP5910/5912, always keep this bit as 1. ‡ Always write 11b to these bits. § This bit must always be kept as 0. Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
Page 41: Initialization
Instruction Cache 4.2.4.3 CAFRZ Bit to Freeze the Contents of the I-Cache When you write 1 to the cache freeze (CAFRZ) bit of ST3_55, the contents of the I-Cache are locked. Instruction words that were cached prior to the freeze are still accessible in the case of an I-Cache hit, but the data arrays are not updated in response to an I-Cache miss.
Page 42: Power Management
Instruction Cache 4.2.8 Power Management If you want to temporarily halt the I-Cache to reduce power, you can place its domain in idle mode: 1) Select the idle mode for the I-Cache domain by making CACHEI = 1 in the idle configuration register (ICR) of the DSP subsystem.
Page 43 Instruction Cache 4.2.10.2 Miss Penalty The miss penalty is the time required for the I-Cache to deliver the 32-bit requested word to the DSP core in the case of a miss (when the word must be fetched from DSP external memory). In response to a miss, the I-Cache requests four words from the external memory interface (EMIF) to load the appropriate line.
Page 44: Configuring The I-Cache With The 2-Way Cache And No Ram Set Blocks
Instruction Cache Configuring the I-Cache With the 2-Way Cache and No RAM Set Blocks The instruction cache is used to store recently-used instructions stored in DSP external memory. The I-Cache automatically fills its 2-way cache with instructions accesses from DSP external memory, in this manner subsequent accesses are essentially fetched from internal memory.
Page 45: Configuring The I-Cache With The 2-Way Cache And One Ram Set
Instruction Cache Configuring the I-Cache With the 2-Way Cache and One RAM Set The instruction cache is used to store recently-used instructions in the DSP external memory. The I-Cache automatically fills its two-way cache with instruction accesses from DSP external memory, thus, subsequent accesses are essentially fetched from internal memory.
Page 46: System Traffic Considerations
Instruction Cache Note: The code that loads the RAM sets cannot be read from DSP external memory at the same time that the RAM sets are being loaded from memory. Therefore, place the RAM-set load code in memory that is internal to the DSP subsystem.
Page 47: Software Configuration
Instruction Cache 4.5.2 Software Configuration Follow this procedure to configure with 2-way cache and two RAM sets: 1) Write to the appropriate control registers: Write CE2Fh to GCR to indicate two RAM sets. Write 000Fh to NWCR to initialize the logic for the 2-way cache. Write 000Fh to RCR1 to initialize the logic for RAM set 1.
Page 48: Summary Of The I-Cache Registers
Note: Not every function documented in these registers is supported on OMAP5910 and OMAP5912. The functions not supported are listed in the section describing each register. Sections 4.3, 4.4, and 4.5 detail the steps needed to correctly configure and initialize the DSP I-Cache in the three supported modes of operation.
Page 49: I-Cache Global Control Register (Gcr)
Note that n ot all functions described in the GCR are supported on OMAP5912 and OMAP5910. For example, the I-Cache supports the 2-way option for the N-way cache and zero, one, or two RAM sets. The following bits must be set...
Page 50: I-Cache Global Control Register (Gcr) Bits Field Descriptions
Instruction Cache Table 6. I-Cache Global Control Register (GCR) Bits Field Descriptions Bits Field Value Description CUT_CLOCK This bit determines whether the I-Cache module clock is disabled or enabled when the I-Cache is disabled. Disabled. Enabled. AUTO_GATING Enables automatic clock gating Disabled.
Page 51: I-Cache Line Flush Registers (Flr0, Flr1)
I-Cache Line Flush Registers (FLR0, FLR1) The I-Cache line flush registers are used to specify the address to be flushed from the cache. Note: These registers are not used, as line flushing is not supported on OMAP5910 and OMAP5912. SPRU890A DSP Subsystem...
Page 52: Cache Line Flush Registers (Flr0, Flr1)
The local flush and enable capabilities of the N-way cache are not supported on OMAP5912 and OMAP5910. Always use the following configuration for the N-way Control Register: FLUSH = 1; the N-way cache is always flushed when CACLR is set.
Page 53: I-Cache N-Way Control Register (Nwcr)
Instruction Cache Figure 14. I-Cache N-Way Control Register (NWCR) Reserved Reserved WAY_SIZE FLUSH ENABLE RW-11 RW-0 RW-1 Note: R = Read, W = Write; −n = Value after reset;, −x = Value after reset is not defined Table 9. I-Cache N-way Control Register (NWCR) Field Descriptions Bits Field Value Description...
Page 54: I-Cache Ram Set Control Registers (Rcr1 And Rcr2)
RAM set, the I-Cache sets TAG_VALID in that RAM set’s control register. You can poll this bit to determine when the RAM set is ready. Note: On OMAP5910 and OMAP5912, you must always set FLUSH and ENABLE in RCR1 and RCR2. Figure 15.
Page 55: (Rcr2) Field Descriptions
Instruction Cache Table 10. I-Cache RAM Set 1 Control Register (RCR1) and RAM Set 2 Control Register (RCR2) Field Descriptions Bits Field Value Description TAG_VALID RAM set tag-valid bit. Check this bit to determine when the I-Cache has completed the process of filling the RAM set. The fill is not started or is not complete.
Page 56: I-Cache Ram Set Tag Registers (Rtr1 And Rtr2)
Instruction Cache Figure 16. I-Cache RAM Set Tag Registers (RTR1 and RTR2) RTR1 R1TAG RW-0 RTR2 R2TAG RW-0 R = Read, W = Write; −n = Value after reset;, −x = Value after reset is not defined Note: Table 11. I-Cache RAM Set 1 Tag Register (RTR1) Field Descriptions Bits Field...
Page 57: I-Cache Status Register (Isr)
Instruction Cache 4.6.7 I-Cache Status Register (ISR) The status register contains the ENABLE bit that indicates when the I-Cache is enabled. When you send an enable request to the I-Cache (CAEN = 1 in the DSP core status register ST3_55), poll for ENABLE = 1 before writing to either of the RAM set tag registers.
Page 58: Dsp External Memory Interface
DSP External Memory Interface DSP External Memory Interface Overview The external memory interface (EMIF) gives the DSP core and the DSP DMA controller access to the shared system memory managed by the traffic controller. The EMIF interfaces directly to a 32-bit-wide system bus. This bus can operate at the DSP subsystem clock rate with sustained throughput during burst accesses.
Page 59: Dsp Subsystem External Memory Connections
DSP External Memory Interface 3) The MMU checks its translation look-aside buffer (TLB, section 6.2.2) for a match on the virtual address tag. If there is a TLB hit and the correct access permissions for the type of access (read or write) are found, the MMU translates the virtual address from the EMIF into a physical address and forwards the request to the traffic controller with the appropriate endianess conversion.
Page 60: Emif Requests And Their Priorities
DSP External Memory Interface 5.2.4 EMIF Requests The EMIF services the requests shown in Table 14. If multiple requests arrive simultaneously, the EMIF prioritizes them as shown in the Priority column. Table 14. EMIF Requests and Their Priorities EMIF Requester Priority Description E bus...
Page 61: Emif Requests Associated With Dual And Long Data Accesses
DSP External Memory Interface Table 15. EMIF Requests Associated with Dual and Long Data Accesses DSP Core Data DSP Core Address Buses Used Bus(es) Used Access Type Request(s) Sent To EMIF Dual data read CB and DB CAB and DAB C-bus request to read 16 bits (carrying two 16-bit values) D-bus request to read 16 bits...
Page 62: Reset Considerations
DSP External Memory Interface 5.2.6 Reset Considerations The EMIF registers can be reset by hardware and software resets. Section 5.3 details the contents of the EMIF configuration registers after reset. 5.2.6.1 Effect of Hardware Reset The EMIF configuration registers are always reset by an OMAP hardware reset.
Page 63: Emif Global Control Register (Gcr)
Global reset register. Use this register to reset the EMIF state 0x0801 5.3.3 machine. † DSP I/O addresses apply to both OMAP5910 and OMAP5912. 5.3.2 EMIF Global Control Register (GCR) The EMIF Global Control Register is used to enable or disable write-posting. Figure 19.
Page 64: Emif Global Reset Register (Grr)
DSP External Memory Interface Table 17. EMIF Global Control Register (GCR) Field Descriptions Bits Field Value Description 15−8 Reserved These bits are not used. Writable bits should be kept as 0 during writes to this register. Write posting enable bit. Use WPE to enable or disable the write posting feature of the EMIF.
Page 65: Memory Defragmentation
DSP Memory Management Unit DSP Memory Management Unit Overview DSP core and DSP DMA accesses to DSP external memory are handled by the DSP external memory interface (EMIF) in conjunction with the DSP Memory Management Unit (MMU). The DSP MMU maps external memory requests to the OMAP physical address space.
Page 66: Task Protection
6.1.2 Features The DSP MMU in OMAP5910 and OMAP5912 devices includes the following features: A translation look-aside buffer (TLB), which stores recently-used translations. The TLB acts like a cache of recently read translation table entries.
Page 67: Dsp Subsystem Memory Interface
DSP Memory Management Unit 6.1.3 Functional Block Diagram Figure 23 shows the role of the DSP MMU within the DSP subsystem memory structure. Figure 23. DSP Subsystem Memory Interface OMAP device DSP subsystem Resources IMIF Requestors Internal SRAM DSP MMU Addr.
Page 68: Mmu Address Translation
DSP Memory Management Unit MMU Architecture 6.2.1 Summary of Address Translation Process As shown in Figure 24, the MMU translates virtual addresses generated by the DSP EMIF to physical addresses. These physical addresses are used to access the actual OMAP resource. Figure 24.
Page 69: Mmu Translation Process
DSP Memory Management Unit Figure 25. MMU Translation Process Translation request Send memory request to traffic controller Access permissions correct Retrieve Translation translation in TLB (Hit) Update (Miss) Read Table translation Descriptors walking tables and valid enabled retrieve descriptor Translation Permission fault fault...
Page 70: Tlb Entry Structure
DSP Memory Management Unit Entries in the TLB can be protected, or locked, against being overwritten if necessary. A maximum of 31 of the 32 TLB entries can be user-written and protected. One entry must always remain unprotected for use by the table walking logic.
Page 71: Determining Virtual Address Tags For Tlb Cam Entries
DSP Memory Management Unit The virtual address tag is a 14-bit field derived from the virtual address of the memory request being processed. Not all the bits in the virtual address tag are needed for translation. Instead, the size of the memory block described by the entry determines the number of bits used.
Page 72 DSP Memory Management Unit The preserved parameter of the TLB entry value determines the behavior of an entry in the event of a TLB flush. If an entry is preserved, it is not deleted upon a TLB global flush. Section 6.2.2.6 describes the TLB flushing mechanism.
Page 73: Determining Physical Address Tags For Tlb Ram Entries
DSP Memory Management Unit Figure 28. Determining Physical Address Tags for TLB RAM Entries Section Physical Page index Section base address address Physical 0 0 0 0 0 0 0 0 0 Section base address address Large page Physical Page index Large page base address address Physical...
Page 74: Physical Address Generation Using Tlb Entry With Size = 00B (Section)
DSP Memory Management Unit 3) Reads the corresponding physical address tag from the TLB entry. 4) Checks the access permission bits. 5) Generates a corresponding physical address by using the physical address tag and the page index (taken from the virtual address). The number of physical address tags and virtual address bits used in this step depends on the size field of the TLB entry.
Page 75: Physical Address Generation Using Tlb Entry With Size = 01B (Large Page)
DSP Memory Management Unit Figure 30. Physical Address Generation Using TLB Entry with Size = 01b (Large Page) DSP virtual address Page index Large page base address Physical address tag Large page base address 0 0 0 0 0 0 Large page base address Page index Physical address...
Page 76: Physical Address Generation Using Tlb Entry With Size = 11B (Tiny Page)
DSP Memory Management Unit Figure 32. Physical Address Generation Using TLB Entry with Size = 11b (Tiny Page) DSP virtual address Page index Tiny page base address Physical address tag Tiny page base address Tiny page base address Page index Physical address 6.2.2.3 Writing Entries to the TLB...
Page 77: Tlb Entry Lock Mechanism
DSP Memory Management Unit 3) Select the TLB entry to be written by setting the victim pointer through the Lock/Protect Entry Register (LOCK_REG). For example, to update entry 0 in the TLB, write 0 to the victim pointer field of LOCK_REG. 4) Set the WRITE_ENTRY bit in the Read/Write TLB Entry Register (LD_TLB_REG).
Page 78 DSP Memory Management Unit entries 0 through 10 of the TLB, write 11 to the base pointer field and load the victim pointer field with a value from 11 to 31. 3) Enable the table walking logic by setting the TWL_EN bit in the Control Register (CNTL_REG).
Page 79: Table Walking Logic
DSP Memory Management Unit bit in the Flush Entry Register (FLUSH_ENTRY_REG). The valid and preserved bits of the TLB entry are cleared when the flush command is completed. To flush individual entries from the TLB, follow these steps: 1) Disable the table walking logic by clearing the TWL_EN bit in the Control Register (CNTL_REG).
Page 80: Physical Address Calculation
DSP Memory Management Unit Figure 34. Physical Address Calculation 20 19 1st level Section view of Section index table index DSP virtual address 1st level translation Address Address table base address Physical address calculator calculator (TTB_HREG, TTB_LREG) 1st level Section base 1st level table descriptor address...
Page 81 DSP Memory Management Unit The table walking logic starts an address translation by accessing a descriptor from a first-level translation table (section 6.2.5). To determine the address of the descriptor, add a first-level table index (taken from the virtual address) and the base address of the first-level translation table (taken from the translation table base registers TTB_MSB_REG and TTB_LSB_REG).
Page 82: Sample Translation Table Hierarchy
DSP Memory Management Unit 6.2.4 Memory Address Translation The table walking logic carries out address translations by accessing a first-level translation table and (if necessary) multiple second-level translation tables. Each translation table is made up of descriptors containing the information needed to map a range of virtual memory addresses to a corresponding range of physical memory addresses.
Page 83: First-Level Translation Table
DSP Memory Management Unit Two types of second-level tables can be used: Coarse page tables with 256 entries. Each entry in a coarse page table contains a descriptor which describes the translation information for either a large page (64KB) or a small page (4KB) of memory.
Page 84: Dsp Subsystem Virtual Address Space Divided Into Sections
DSP Memory Management Unit If MPNMC in ST3_55 is 0, the virtual memory address range 0xFF 8000 through 0xFF FFFF will be mapped to the DSP subsystem internal PDROM. Conversely, if MPNMC = 1, the internal PDROM will be disabled and the addresses will be mapped to external memory.
Page 85: First-Level Descriptor Address Calculation
DSP Memory Management Unit The 25 most-significant bits of the first-level translation table start address are called the translation table base. The translation table base is set by writing to the MMU Translation Table Registers (TTB_H_REG and TTB_L_REG). The four most-significant bits of the DSP virtual address are called the table index. The translation table base and the table index are used to calculate the address of the first-level descriptor (see Figure 37).
Page 86: First-Level Descriptor Format Based On Two Least-Significant Bits
DSP Memory Management Unit Figure 38. First-Level Descriptor Format Based on Two Least-Significant Bits Fault Pointer to course page table 10 9 Course page table base address Pointer to section in physical memory 20 19 Section base address Pointer to fine page table 12 11 Fine page table base address Legend: AP = Access Permissions: 00 or 01 = no access, 10 = read only, 11 = full access;...
Page 87: Translation For A Virtual Memory Section
DSP Memory Management Unit 6.2.5.2 Translating Sections When the first-level descriptor contains a pointer to a section in physical memory, the section base address contained in the descriptor is used to calculate the physical memory address for the original DSP virtual address (Figure 39).
Page 88: Second-Level Descriptor Format Based On Two Least-Significant Bits
DSP Memory Management Unit Both types of page tables contain second-level descriptors which provide the translation information for a large page, a small page, or a tiny page. Note that the format of the second-level descriptor is the same regardless of the type of second-level page table in which it is used.
Page 89: Translation For A Large Page
DSP Memory Management Unit Table 20. First−Level Descriptor Contents Least-Significant Descriptor Contents Meaning Two Bits of Des- criptor Contents Any access to the page in virtual memory corresponding to this descriptor will generate a fault. As described in section 6.2.7, the fault error must be addressed by the MPU core.
Page 90: Translation For A Small Page
DSP Memory Management Unit 6.2.6.3 Translating Small Pages Figure 42 describes how the contents of a small page descriptor are used to calculate the physical address of the DSP virtual address. Figure 42. Translation for a Small Page Second-level descriptor contents 12 11 Small page base address DSP virtual address...
Page 91: Calculating The Descriptor Address In A Coarse
DSP Memory Management Unit 6.2.6.5 Coarse Page Tables Coarse page tables can be used to map large and small pages of virtual memory to physical memory. Each coarse table must contain 256 entries. Follow these rules when using coarse page tables: The start address of a coarse page table must be aligned on a 1024-byte boundary;...
Page 92: Calculating The Descriptor Address In A Fine Page Table
DSP Memory Management Unit As described in section 6.2.2, the TLB can be used to bypass the translation tables. Using this approach, only one TLB entry is required to translate a large page. 6.2.6.6 Fine Page Tables Fine page tables can be used to map large, small, and tiny pages of virtual memory to physical memory.
Page 93: Mmu Error Handling
DSP Memory Management Unit Notice that the MMU indexes the coarse table as if the entries were specifying tiny pages. That is, it always selects 1 of 1024 entries. However, the MMU uses 16 bits from the second−level descriptor as a base address for a large page and 22 bits for a tiny page (see Figure 41 and Figure 43, respectively).
Page 94: Reset Considerations
DSP Memory Management Unit Note: The DSP EMIF will be stalled, thus stalling the original requestor (either the DSP core or DMA), while the error is cleared by the MPU core. The ISR can service each error as follows: For a pre-fetch or translation fault, the ISR must write a valid entry to the TLB and acknowledge the interrupt through the interrupt acknowledge register (IT_ACK_REG).
Page 95: Clock Control
DSP Memory Management Unit 6.2.9 Clock Control The DSP MMU module is clocked by the DSPMMU_CK included in the DSP clock domain. The DSP domain clock can be divided by 1, 2, 4, or 8 to generate the MMU clock by using the DSPMMUDIV bits of the ARM_CKCTL register. By default, the DSPMMUDIV bits are set to divide-by-one mode.
Page 96: Power Management
DSP Memory Management Unit 6.2.12 Power Management The clock to the DSP MMU can be shut off to save power. The GL_PDE bit of the DSPMMU_IDLE_CTRL register can be set to completely shut off the clock to the DSP MMU. Alternatively, the AUTOGATING_EN bit can be set such that the clock to the DSP MMU is only shut off when DSP MMU is not active.
Page 97: Dsp Subsystem External Memory Interface
DSP Memory Management Unit Figure 46. DSP Subsystem External Memory Interface OMAP device DSP subsystem Resources IMIF Requestors Internal SRAM DSP MMU Addr. Addr. Traffic DSP core Address controller data buses conversion EMIFS Data Data Flash Endianess DSP core conversion program buses EMIFF Access...
Page 98: System Traffic Considerations
DSP Memory Management Unit 4) Configure the MPU level 2 interrupt handler such that DSP MMU interrupts are enabled and can be serviced by the MPU core. More information on the MPU level 2 interrupt handler can be found in the OMAP5912 Multimedia Processor Interrupts Reference Guide (SPRU757).
Page 99: Dsp Subsystem External Memory Interface
DSP Memory Management Unit 3) The MMU checks its TLB for a match on the virtual address tag. If there is a TLB hit and the correct access permissions for the type of access (read or write) are found, the MMU translates the virtual address from the EMIF into a physical address and forwards the request to the traffic controller with the appropriate endianess conversion.
Page 100: System Traffic Considerations
DSP Memory Management Unit The MPU core must follow these steps to initialize and enable the DSP MMU: 1) Set up the translation tables. The translation tables can be placed anywhere in shared memory (CS0, CS1, etc.). Depending on the table structure selected, one or more tables may be needed.
Page 101: Summary Of Dsp Mmu Registers
RAM value to be written to the entry pointed to by the 0xFFFE D238 victim pointer. † MPU byte addresses apply to both OMAP5910 and OMAP5912. ‡ This register is accessible by the DSP core at I/O address 0x4400. SPRU890A...
Page 102: Mmu Pre-Fetch Register (Prefetch_Reg)
MMU Idle Control register. Use this register to control 0xFFFE D254 6.5.17 the power-down capabilities of the DSP MMU. † MPU byte addresses apply to both OMAP5910 and OMAP5912. ‡ This register is accessible by the DSP core at I/O address 0x4400. 6.5.2 MMU Pre-Fetch Register (PREFETCH_REG) The table walking logic automatically fetches an entry for the TLB when a TLB miss is generated.
Page 103: Mmu Pre-Fetch Register (Prefetch_Reg)
DSP Memory Management Unit Figure 48. MMU Pre-Fetch Register (PREFETCH_REG) DSP Side Reserved PREFETCH_ADDR MPU Side Reserved PREFETCH_ADDR R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined. Note: Table 22. MMU Pre-Fetch Register (PREFETCH_REG) Field Descriptions Bits Field Value Description...
Page 104: Mmu Pre-Fetch Status Register (Walking_St_Reg)
DSP Memory Management Unit Table 23. MMU Pre-Fetch Status Register (WALKING_ST_REG) Field Descriptions Bits Field Value Description 31−2 These bits are not used. Reserved This bit is used to indicate when the table walking logic is performing WALK_WORKING an address translation after a miss in the TLB. Table walking logic is not performing any action.
Page 105: Control Register (Cntl_Reg) Field Descriptions
DSP Memory Management Unit Table 24. Control Register (CNTL_REG) Field Descriptions Bits Field Value Description 31−3 Reserved These bits are not used. TWL_EN Enables the table walking logic. Note: When the table walking logic is enabled, the TLB cannot be manually updated;...
Page 106: Mmu Msb Fault Address Register (Fault_Ad_H_Reg) Field Descriptions
DSP Memory Management Unit Figure 51. MMU Fault Address Registers (FAULT_AD_H_REG, FAULT_AD_L_REG) FAULT_AD_H_REG Reserved FAULT_ADDRESS_MSB RW-0 FAULT_AD_L_REG Reserved FAULT_ADDRESS_LSB RW-0 R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined. Note: Table 25.
Page 107: Mmu Fault Status Register (Fault_St_Reg)
DSP Memory Management Unit 6.5.6 MMU Fault Status Register (FAULT_ST_REG) When an error is generated by the MMU, the MMU Fault Status Register (FAULT_ST_REG) determines the cause of the error. The MMU generates errors based on the following conditions: TLB miss (table walker disabled): No translation is found in the TLB for the virtual address issued.
Page 108: Mmu Interrupt Acknowledge Register (It_Ack_Reg)
DSP Memory Management Unit Table 27. MMU Fault Status Register (FAULT_ST_REG) Field Descriptions (Continued) Bits Field Value Description PERM_FAULT This bit indicates when the DSP core attempted to access a section/page without the proper access permissions. No permission fault exists. A permission fault has been generated.
Page 109: Mmu Interrupt Acknowledge Register (It_Ack_Reg)
DSP Memory Management Unit Table 28. MMU Interrupt Acknowledge Register (IT_ACK_REG) Field Descriptions Bits Field Value Description 31−1 Reserved These bits are not used. IT_ACK The MPU core must write a 1 to this bit to acknowledge the interrupt from the DSP MMU. Writing 0 has no effect.
Page 110: Mmu Msb Translation Table Register (Ttb_H_Reg) Field Descriptions
DSP Memory Management Unit Table 29. MMU MSB Translation Table Register (TTB_H_REG) Field Descriptions Bits Field Value Description 31−16 Reserved These bits are not used. 15−0 TTB_H 0x0000− Most-significant bits of the 25-bit base address of the first-level 0xFFFF translation table. Table 30.
Page 111: Mmu Lock/Protect Entry Register (Lock_Reg)
DSP Memory Management Unit Table 31. MMU Lock/Protect Entry Register (LOCK_REG) Field Descriptions Bits Field Value Description 31−15 Reserved These bits are not used. Always write 0 to these bits. 14−10 BASE_VALUE 0−31 TLB lock base pointer. The value, n, that is written to these bits locks the first n TLB entries.
Page 112: Mmu Read/Write Tlb Entry Register (Ld_Tlb_Reg)
DSP Memory Management Unit Table 32. MMU Read/Write TLB Entry Register (LD_TLB_REG) Field Descriptions Bits Field Value Description 31−2 Reserved These bits are not used. READ_ENTRY Read the TLB entry. Writing 1 to this field causes an entry to be read from the TLB.
Page 113: Mmu Msb Cam Entry Register (Cam_H_Reg) Field Descriptions
DSP Memory Management Unit Table 33. MMU MSB CAM Entry Register (CAM_H_REG) Field Descriptions Bits Field Value Description 31−2 Reserved These bits are not used. 1−0 VA_TAG_H 0x0− Most-significant bits of the virtual address tag. The VA_TAG bits correspond to bits 23−10 of the DSP virtual address. Note that, depending on the page size, not all of the VA_TAG bits are needed;...
Page 114: Mmu Msb Ram Entry Register (Ram_H_Reg) Field Descriptions
DSP Memory Management Unit 6.5.12 MMU RAM Entry Registers (RAM_H_REG, RAM_L_REG) The RAM Entry Registers specify a RAM value to be written into the TLB. Figure 58. MMU RAM Entry Registers (RAM_H_REG, RAM_L_REG) RAM_H_REG Reserved PHYS_TAG_H RW-0 RAM_L_REG Reserved PHYS_TAG_L Reserved RW-0 RW-0...
Page 115: Mmu Tlb Global Flush Register (Gflush_Reg)
DSP Memory Management Unit Table 36. MMU LSB RAM Entry Register (RAM_L_REG) Field Descriptions (Continued) Bits Field Value Description 9−8 Access permission bits. These bits determine the access permission for the physical memory covered by the TLB entry. 00 or No access.
Page 116: Mmu Tlb Entry Flush Register (Flush_Entry_Reg)
DSP Memory Management Unit 6.5.14 MMU TLB Entry Flush Register (FLUSH_ENTRY_REG) The TLB Entry Flush Register deletes individual entries from the TLB. When the FLUSH_ENTRY bit is set, the preserved and valid bits of the entry pointed to by the victim pointer are cleared. Figure 60.
Page 117: Mmu Cam Entry Read Registers (Read_Cam_H_Reg, Read_Cam_L_Reg)
DSP Memory Management Unit 6.5.15 MMU Read CAM Entry Registers (READ_CAM_H_REG, READ_CAM_L_REG) The Read CAM Entry Registers hold the last CAM value read from the TLB. Figure 61. MMU CAM Entry Read Registers (READ_CAM_H_REG, READ_CAM_L_REG) READ_CAM_H_REG Reserved Reserved VA_TAG_H READ_CAM_L_REG Reserved VA_TAG_L PRE-...
Page 118: Mmu Lsb Cam Entry Read Register (Read_Cam_L_Reg) Field Descriptions
DSP Memory Management Unit Table 40. MMU LSB CAM Entry Read Register (READ_CAM_L_REG) Field Descriptions Bits Field Value Description 31−16 Reserved These bits are not used. 15−4 VA_TAG_L Least-significant bits of the virtual address tag. The VA_TAG bits correspond to bits 23−10 of the DSP virtual address. PRESERVED Preserve bit for the TLB entry.
Page 119: Mmu Read Ram Entry Registers (Read_Ram_H_Reg, Read_Ram_L_Reg)
DSP Memory Management Unit 6.5.16 MMU Read RAM Entry Registers (READ_RAM_H_REG, READ_RAM_L_REG) The Read RAM Entry Registers hold the last RAM value read from the TLB. Figure 62. MMU Read RAM Entry Registers (READ_RAM_H_REG, READ_RAM_L_REG) READ_RAM_H_REG Reserved PHYS_TAG_H READ_RAM_L_REG Reserved PHYS_TAG_L Reserved Note:...
Page 120: Mmu Idle Control Register (Dspmmu_Idle_Ctrl)
DSP Memory Management Unit Table 42. MMU LSB RAM Entry Read Register (READ_RAM_L_REG) Field Descriptions Bits Field Value Description 31−16 Reserved These bits are not used. 15−10 PHYS_TAG_L These are the least-significant bits of the physical address tag corresponding to the TLB entry. The PHYS_TAG bits correspond to bits 31−10 of the physical memory address.
Page 121: Overview
DSP DMA DSP DMA Overview 7.1.1 Purpose of the DSP DMA Acting in the background of DSP core operation, the DMA controller can: Transfer data among internal memory, DSP external memory, and peripherals residing on the DSP public peripheral bus Transfer data between the Microprocessor Unit Interface (MPUI) and memory internal to the DSP subsystem 7.1.2...
Page 122: Block Diagram Of The Dma Controller
DSP DMA 7.1.3 Block Diagram of the DMA Controller Figure 64 is a conceptual diagram of connections between the DMA controller and other parts of the DSP subsystem. The DMA controller ports in the diagram are: Four standard ports. The DMA controller has a standard port for each of the following resources: internal dual-access RAM (DARAM), internal single-access RAM (SARAM), DSP external memory, and peripherals.
Page 123: Conceptual Block Diagram Of The Dma Controller Connections
DSP DMA Figure 64. Conceptual Block Diagram of the DMA Controller Connections MPU subsystem DSP subsystem MPUI port Port Port DARAM MPUI Port SARAM DSP public peripheral bus controller Shared TIPB Port Peripherals MPU core bridge Channels System Port EMIF 0−5 Endianess conversion Traffic...
Page 124: High-Level Data Memory Map For Dsp Subsystem
DSP DMA DSP DMA Controller Architecture 7.2.1 Clock Control The DSP DMA controller is part of the DSP module within the DSP subsystem (see section 1.2) and thus is clocked by the DSP subsystem clock, DSP_CK. Section 12.2 describes the DSP subsystem clock. 7.2.2 Memory Map Figure 65 is a high-level memory map for the DSP subsystem data memory...
Page 125: High-Level I/O Memory Map For Dsp Subsystem
DSP DMA Note: The I/O memory map varies from device to device due to the different mixes of peripherals. For a detailed I/O memory map, see the device-specific data manual. Figure 66. High-Level I/O Memory Map for DSP Subsystem Word addresses Byte addresses (Hexadecimal range) I/O space...
Page 126: Registers For Controlling The Context Of A Channel
DSP DMA The set of conditions under which transfers occur in a channel is called the channel context. Each of the six channels contains a register structure for programming and updating the channel context (see Figure 68). The programming code modifies the configuration registers. When it is time for data transferring, the contents of the configuration registers are copied to the working registers, and the DMA controller uses the working register values to control channel activity.
Page 127: Dma Channel Control Register (Dmaccr)
DSP DMA 7.2.4 Channel Auto-Initialization Capability After a block transfer is completed (all of the elements and frames in a block have been moved), the DMA controller automatically disables the channel. If the channel must be used again, the DSP core can reprogram the new channel context and re-enable the DMA channel, or the DMA controller can automatically initialize the new context and re-enable the channel.
Page 128: Dma Channel Control Register (Dmaccr) Field Descriptions
DSP DMA Table 44. DMA Channel Control Register (DMACCR) Field Descriptions Bits Field Value Description 15−12 Reserved Reserved ENDPROG End-of-programming bit. Each DMA channel has two sets of registers: configuration registers and working registers. When block transfers occur repeatedly because of auto-initialization (AUTOINIT = 1), you can change the context for the next DMA transfer by writing to the configuration registers during the current block transfer.
Page 129 DSP DMA Table 44. DMA Channel Control Register (DMACCR) Field Descriptions (Continued) Bits Field Value Description REPEAT Repeat condition bit. If auto-initialization is selected for a channel (AUTOINIT = 1), REPEAT specifies one of two special repeat conditions: Repeat only if ENDPROG = 1. Once the current DMA transfer is complete, auto-initialization will wait for the end-of-programming bit (ENDPROG) bit to be set.
Page 130: Auto-Initialization Sequence With Unchanging Context (Repeat = 1)
DSP DMA Figure 70. Auto-Initialization Sequence With Unchanging Context (REPEAT = 1) The DSP core programs desired channel context into the configuration registers The DSP core sets AUTOINIT=1 and REPEAT=1 to select the correct auto-initialization mode The DMA controller The DSP core sets EN=1 transfers the block of data to enable the DMA channel according to the channel...
Page 131: Auto-Initialization Sequence With Changing Context (Repeat = 0)
DSP DMA Figure 71. Auto-initialization Sequence With Changing Context (REPEAT = 0) ENDPROG = 0 after reset The DSP core sets AUTOINIT=1 and clears REPEAT= 0 to select the correct auto-initialization mode DMA detects ENDPROG = 1 The DSP core programs the desired channel context for the first block transfer into the configuration registers and enables the channel...
Page 132: Service Chain
DSP DMA Figure 72. MPUI Access Configurations MPUI EXCL = 0 Port read/write Port read/write requests requests MPUI DARAM port DMA channels SARAM port External memory port Peripheral port MPUI EXCL = 1 Port read/write Port read/write requests requests MPUI DARAM port DMA channels SARAM port...
Page 133: One Possible Configuration For The Service Chains
DSP DMA Section 7.2.6.1 contains an example that shows a service chain configuration applied to three ports. Figure 73. One Possible Configuration for the Service Chains High priority High priority High priority Channel Channel Channel Channel Channel Channel MPUI Low priority Low priority Low priority Low priority...
Page 134 DSP DMA The channels can be individually connected or disconnected from the service chain through software. If a channel is enabled (EN = 1 in DMACCR), it is connected to the service chain; if it is disabled (EN = 0), it is disconnected.
Page 135: Activity Shown In
DSP DMA Table 45 summarizes the activity at the ports in Figure 74. Table 45. Activity Shown in Figure 74 Port This Port Arbitrates DARAM Write access requests from channel 2 Read access requests from channel 4 Read or write access requests from the MPUI External Memory Write access requests from channel 1 Write access requests from channel 4...
Page 136: Service Chain Applied To Three Dma Ports
DSP DMA Figure 74. Service Chain Applied to Three DMA Ports Configuration for High-priority: 0, 2, 5 Disabled: 0, 3, 5 MPUI shares with channels the service chains Low-priority: 1, 3, 4, MPUI Enabled: 1, 2, 4 DARAM port: Only used by channel 2, channel 4, and MPUI MPUI Ch 0 Ch 2...
Page 137: Registers Used To Define The Start Addresses For A Dma Transfer
DSP DMA 7.2.7 Units of Data: Byte, Element, Frame, and Block This documentation on the DMA controller refers to data in four levels of granularity: Byte: An 8-bit value. A byte is the smallest unit of data transferred in a DMA channel.
Page 138 DSP DMA 7.2.8.1 Start Address in DSP Subsystem Data Memory Figure 65 is a high-level memory map for the DSP subsystem. The diagram shows both the word addresses (23-bit addresses) used by the DSP core and byte addresses (24-bit addresses) used by the DMA controller. To load the source/destination start address registers: 1) Identify the correct start address.
Page 139: Dma Controller Ports
DSP DMA 7.2.9 Updating Addresses in a Channel During data transfers in a DMA channel, the DMA controller begins its read and write accesses at the start addresses you specify (see section 7.2.8). In many cases, these addresses must be updated so that data is read and written at consecutive or indexed locations after a data transfer has begun.
Page 140: Dma Controller Data Packing
DSP DMA A DMA channel has the ability to pack and unpack. Pack: Pack several consecutive element transfers into wider accesses. For example, if the element size is 16 bits, the 32-bit-wide SARAM port can pack two accesses so that 4 bytes at a time are written into the channel FIFO.
Page 141: Data Burst Capability
DMA controller will perform four single peripheral port accesses to move the burst data. More information on the traffic controller interfaces can be found in the OMAP5910 Dual-Core Processor Memory Interface Traffic Controller Reference Guide (SPRU673) and the OMAP5912 Multimedia Processor OMAP3.2 Subsystem Reference...
Page 142: Synchronizing Channel Activity
DSP DMA 7.2.12 Synchronizing Channel Activity Activity in a channel can be synchronized to a request from a DSP public peripheral or MPU/DSP shared peripheral. Each peripheral request is tied to a DMA synchronization event. You can use a DMA synchronization event to trigger channel activity using the SYNC bits of DMACCR.
Page 143: Read/Write Synchronization
DSP DMA There are three general cases (see Table 49). Case 1: Source port is peripheral; destination port is SARAM, DARAM, or EMIF. The channel waits for the synchronization event before reading from the peripheral port into the channel FIFO (source synchronization). Once the FIFO is filled, the DMA channel begins writing to the destination port to empty the FIFO.
Page 144 DMACCR to the value listed in these tables. Note: On the OMAP5910, the synchronization events of the DSP DMA controller are tied to the peripheral requests specified in Table 50. However, on the OMAP5912, the source for each synchronization event can be changed using the DSP GDMA Handler, as described in section 7.2.13.
Page 145: Dsp Dma Controller Synchronization Events For Omap5910
DSP DMA Table 50. DSP DMA Controller Synchronization Events for OMAP5910 DMA Event Generated By (On OMAP5910): Setting For SYNC Bits DMA_EVT1 MCSI1 Transmit Request (MCSI1TX) 00001b DMA_EVT2 MCSI1 Receive Request (MCSI1RX) 00010b DMA_EVT3 MCSI2 Transmit Request (MCSI2TX) 00011b DMA_EVT4...
Page 146: Dsp Dma Controller Synchronization Events For Omap5912
DSP DMA Table 51. DSP DMA Controller Synchronization Events for OMAP5912† DMA Event Generated By (On OMAP5912): Setting For SYNC Bits DMA_EVT1 MCSI1 Transmit Request (MCSI1TX) 00001b DMA_EVT2 MCSI1 Receive Request (MCSI1RX) 00010b DMA_EVT3 MCSI2 Transmit Request (MCSI2TX) 00011b DMA_EVT4 MCSI2 Receive Request (MCSI2RX) 00100b DMA_EVT5...
Page 147: Dsp Gdma Handler
DSP DMA Figure 75. DSP GDMA Handler MPU and shared peripherals PERIPH_REQ28 PERIPH_REQ1 GDMA Handler registers MPU GDMA Handler DMA_EVT1 DMA_EVT19 DSP DMA Table 52 lists the source of the 28 input lines of the GDMA Handler. Table 52. DSP GDMA Handler Input Request Lines Input Request Line Generated By: PERIPH_REQ1...
Page 148 DSP DMA Table 52. DSP GDMA Handler Input Request Lines (Continued) Input Request Line Generated By: PERIPH_REQ19 UART3 Receive Request (UART3RX) PERIPH_REQ20 CMT-APE Transmit Request , channel 1 (CMTAPE1TX) PERIPH_REQ21 CMT-APE Receive Request, channel 1 (CMTAPE1RX) PERIPH_REQ22 CMT-APE Transmit Request, channel 2 (CMTAPE2TX) PERIPH_REQ23 CMT-APE Receive Request, channel 2 (CMTAPE2RX) PERIPH_REQ24...
Page 149: Registers Of The Omap5912 Dsp Gdma Handler
DSP DMA 7.2.13.3 Registers Table 53 lists the registers associated with the OMAP5912 DSP GDMA Handler. These registers can be accessed by the MPU through the OMAP15912 configuration module. The descriptions for each register follow the table. Table 53. Registers of the OMAP5912 DSP GDMA Handler MPU Byte Address Name...
Page 150: Field Descriptions
DSP DMA Figure 76. Functional Multiplexing DSP DMA Register A (FUNC_MUX_DSP_DMA_A) Reserved CONF_DSP_DMA_EVT_06 RW-0 RW-0x05 CONF_DSP_DMA_EVT_05 CONF_DSP_DMA_EVT_04 RW-0x04 RW-0x03 CONF_DSP_DMA_EVT_03 CONF_DSP_DMA_ EVT_02 RW-0x02 RW-0x01 CONF_DSP_DMA_EVT_02 CONF_DSP_DMA_EVT_01 RW-0x01 RW-0x00 Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined. Table 54.
Page 151: Functional Multiplexing Dsp Dma Register B (Func_Mux_Dsp_Dma_B)
DSP DMA Table 54. Functional Multiplexing DSP DMA Register A (FUNC_MUX_DSP_DMA_A) Field Descriptions (Continued) Bits Field Value Description 9−5 CONF_DSP_DMA_ 0−27 Configuration bits for DMA event 2. Writing a value n to this EVT_02 register maps peripheral request source n+1 to DSP DMA event 2.
Page 152: Field Descriptions
DSP DMA Table 55. Functional Multiplexing DSP DMA Register B (FUNC_MUX_DSP_DMA_B) Field Descriptions Bits Field Value Description 31−30 Reserved These read-only bits return 0s when read. 29−25 CONF_DSP_DMA_ 0−27 Configuration bits for DMA event 12. Writing a value n to this EVT_12 register maps peripheral request source n+1 to DSP DMA event 12.
Page 153: Field Descriptions
DSP DMA Figure 78. Functional Multiplexing DSP DMA Register C (FUNC_MUX_DSP_DMA_C) Reserved CONF_DSP_DMA_EVT_18 CONF_DSP_ DMA_EVT_17 RW-0 RW-0x11 RW-0x10 CONF_DSP_DMA_EVT_17 CONF_DSP_DMA_EVT_16 RW-0x10 RW-0x0F CONF_DSP_ CONF_DSP_DMA_EVT_15 CONF_DSP_DMA_ DMA_EVT_16 EVT_14 RW-0x0F RW-0x0E RW-0x0D CONF_DSP_DMA_EVT_14 CONF_DSP_DMA_EVT_13 RW-0x0D RW-0x0C Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined. Table 56.
Page 154: Reset Considerations
DSP DMA Bits Field Value Description 9−5 CONF_DSP_DMA_ 0−27 Configuration bits for DMA event 14. Writing a value n to this EVT_14 register maps peripheral request source n+1 to DSP DMA event 14. The value n must be between 0 and 27. 4−0 CONF_DSP_DMA_ 0−27...
Page 155: Dma Controller Operational Events And Their Associated Bits And Interrupts
DSP DMA 7.2.15 Interrupt Support The DMA controller can send an interrupt to the DSP core in response to the operational events listed in Table 58. Each channel has interrupt enable (IE) bits in the interrupt control register (DMACICR) and some corresponding status bits in the status register (DMACSR).
Page 156: Triggering A Channel Interrupt Request
DSP DMA 7.2.15.1 Channel Interrupt Each of the six channels has its own interrupt. As shown in Figure 80, the channel interrupt is the logical OR of all the enabled operational events except the timeout event (the timeout event generates a bus-error interrupt request). You can choose any combination of these five events by setting or clearing the appropriate interrupt enable (IE) bits in the interrupt control register (DMACICR) for the channel.
Page 157 Interrupt Handler. A timeout event generates a bus error interrupt to the DSP core. For more information on the DSP subsystem interrupt handlers, see the OMAP5910 Dual-Core Processor DSP Subsystem Interrupts Reference Guide (SPRU923) or the OMAP5912 Multimedia Processor Interrupts Reference Guide (SPRU757).
Page 158: Power Management
DSP DMA In response to a timeout signal, the DMA controller disables the channel (EN = 0 in DMACCR) and activity in the channel stops. If the corresponding interrupt enable bit is set (TIMEOUTIE = 1 in DMACICR), the DMA controller also sets the timeout status bit (TIMEOUT = 1 in DMACSR) and sends the timeout signal to the DSP core as an interrupt request.
Page 159: Latency In Dma Transfers
DSP DMA 7.2.18 Latency in DMA Transfers Each element transfer in a channel is composed of a read access (a transfer from the source location to the channel buffer) and a write access (a transfer from the channel buffer to the destination location). The time to complete this activity depends on factors such as: The selected frequency of the DSP core clock signal.
Page 160: Registers Of The Dma Controller
DSP DMA DSP DMA Controller Registers 7.3.1 Overview Table 59 lists the types of registers in the DMA controller. There are three global control registers (DMAGCR, DMAGSCR, and DMAGTCR) that affect all channel activity. In addition, for each of the DMA channels, there are individual channel configuration registers.
Page 161: Dma Global Control Register (Dmagcr)
DSP DMA 7.3.2 DMA Global Control Register (DMAGCR) The global control register (see Figure 81 and Table 60) is a 16-bit read/write register. Use this I/O-mapped register to set the emulation mode of the DMA controller (FREE) and to define how the DMA controller treats the host port interface (MPUI_EXCL and MPUI_PRIO).
Page 162: Dma Global Software Compatibility Register (Dmagscr)
DSP DMA Table 60. DMA Global Control Register (DMAGCR) Field Descriptions (Continued) Bits Field Value Description MPUI_PRIO MPUI priority bit. MPUI_PRIO assigns the MPUI a high or low priority level in the service chain of the DMA controller. Note: When the MPUI has exclusive access to the DARAM and SARAM ports (MPUI_EXCL = 1), the MPUI priority is irrelevant at these ports because none of the DMA channels can access the DARAM and SARAM ports.
Page 163: Dma Global Timeout Control Register (Dmagtcr)
DSP DMA Table 61. DMA Global Software Compatibility Register (DMAGSCR) Field Descriptions Bits Field Value Description 15−1 Reserved These read-only bits return 0s when read. DINDXMD Destination element and frame index mode bit. This bit determines which registers will be used to indicate the destination element and frame indexes.
Page 164: Dma Global Timeout Control Register (Dmagtcr) Field Descriptions
DSP DMA Table 62. DMA Global Timeout Control Register (DMAGTCR) Field Descriptions Bits Field Value Description 15−2 Reserved These read-only bits return 0s when read. DTCE DARAM timeout counter enable bit. This bit enables/disables the timeout counter used to monitor delays on DMA requests to the DARAM port.
Page 165: Dma Channel Control Register (Dmaccr)
DSP DMA Figure 84. DMA Channel Control Register (DMACCR) DSTAMODE SRCAMODE ENDPROG Reserved † REPEAT AUTOINIT RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 PRIO SYNC RW-0 RW-0 RW-0 RW-0 † Bit 10 must be kept 0 for proper operation of the DMA controller. Note: R = Read;...
Page 166 DSP DMA Table 63. DMA Channel Control Register (DMACCR) Field Descriptions (Continued) Bits Field Value Description 13−12 SRCAMODE Source addressing mode bits. SRCAMODE determines the addressing mode used by the DMA controller when it reads from the source port of the channel. At the end of a transfer, but before any incrementing, the source address is the address of the last byte that was read from the source.
Page 167 DSP DMA Table 63. DMA Channel Control Register (DMACCR) Field Descriptions (Continued) Bits Field Value Description ENDPROG End-of-programming bit. Each DMA channel has two sets of registers: configuration registers and working registers. When block transfers occur repeatedly because of auto-initialization (AUTOINIT = 1), you can change the context for the next DMA transfer by writing to the configuration registers during the current block transfer.
Page 168 DSP DMA Table 63. DMA Channel Control Register (DMACCR) Field Descriptions (Continued) Bits Field Value Description REPEAT Repeat condition bit. If auto-initialization is selected for a channel (AUTOINIT = 1), REPEAT specifies one of two special repeat conditions: Repeat only if ENDPROG = 1. Once the current DMA transfer is complete, auto-initialization will wait for the end-of-programming bit (ENDPROG) bit to be set.
Page 169 DSP DMA Table 63. DMA Channel Control Register (DMACCR) Field Descriptions (Continued) Bits Field Value Description PRIO Channel priority bit. All six of the DMA channels are given a fixed position and programmable priority level on the service chain of the DMA controller.
Page 170 DSP DMA 7.3.6 DMA Interrupt Control Register (DMACICR) and Status Register (DMACSR) Each channel has an interrupt control register (DMACICR) and a status register (DMACSR). DMACICR and DMACSR are I/O-mapped registers. Their bits are shown in Figure 85 and described in Table 64 and Table 65. Use DMACICR to specify if one or more operational events in the DMA controller trigger an interrupt.
Page 171: Dma Interrupt Control Register (Dmacicr) And Status Register (Dmacsr)
DSP DMA Figure 85. DMA Interrupt Control Register (DMACICR) and Status Register (DMACSR) DMACICR Reserved Reserved BLOCKIE LASTIE FRAMEIE HALFIE DROPIE TIMEOUTIE RW-0 RW-0 RW-0 RW-0 RW-1 RW-1 DMACSR Reserved Reserved SYNC BLOCK LAST FRAME HALF DROP TIMEOUT Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined. Table 64.
Page 172 DSP DMA Table 64. DMA Interrupt Control Register (DMACICR) Fields Descriptions (Continued) Bits Field Value Description FRAMEIE Whole frame interrupt enable bit. FRAMEIE determines how the DMA controller responds when the all of the current frame has been transferred from the source port to the destination port. Do not record the event.
Page 173: Dma Status Register (Dmacsr) Field Descriptions
DSP DMA Table 65. DMA Status Register (DMACSR) Field Descriptions Bits Field Value Description 15−7 Reserved These read-only bits returns 0s when read. SYNC Synchronization event status bit. The DMA controller updates SYNC to indicate when the synchronization event for the channel has occurred or when the synchronized channel has been serviced.
Page 174: Dma Source And Destination Parameters Register (Dmacsdp)
DSP DMA Table 65. DMA Status Register (DMACSR) Field Descriptions (Continued) Bits Field Value Description HALF Half frame status bit. The DMA controller sets HALF only if HALFIE = 1 in DMACICR and the first half of the current frame has been transferred from the source port to the destination port.
Page 175: Dma Source And Destination Parameters Register (Dmacsdp)
DSP DMA Figure 86. DMA Source and Destination Parameters Register (DMACSDP) DSTBEN DSTPACK SRCBEN RW-0 RW-0 RW-0 RW-0 SRCBEN SRCPACK DATATYPE RW-0 RW-0 RW-0 RW-0 Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined. Table 66.
Page 176 DSP DMA Table 66. DMA Source and Destination Parameters Register (DMACSDP) Field Descriptions (Continued) Bits Field Value Description 12−9 Destination selection bits. DST selects which DMA port is the destination for data transfers in the channel. 0000b SARAM (single-access RAM inside the DSP subsystem). 0001b DARAM (dual-access RAM inside the DSP subsystem).
Page 177 DSP DMA Table 66. DMA Source and Destination Parameters Register (DMACSDP) Field Descriptions (Continued) Bits Field Value Description SRCPACK Source packing enable bit. The DMA controller can perform data packing to double or quadruple the amount of data gathered at the source before a transfer.
Page 178 DSP DMA Table 66. DMA Source and Destination Parameters Register (DMACSDP) Field Descriptions (Continued) Bits Field Value Description 1−0 DATATYPE Data type bits. DATATYPE indicates how data is to be accessed at the source and at the destination of the channel. Note that the DMA controller uses byte addresses for its accesses;...
Page 179: Dma Source Start Address Registers (Dmacssau And Dmacssal)
DSP DMA 7.3.8 DMA Source Start Address Registers (DMACSSAU and DMACSSAL) Each channel has two source start address registers, which are shown in Figure 87 and described in Table 68 and Table 67. For the first access to the source port of the channel, the DMA controller generates a byte address by concatenating the contents of these two I/O-mapped registers.
Page 180: Dma Destination Start Address Registers (Dmacdsau And Dmacdsal)
DSP DMA Table 67. DMA Source Start Address Register − Upper Part (DMACSSAU) Field Descriptions Bits Field Value Description 15−0 SSAU 0000h− Upper part of source start address (byte address). 00FFh 0100h− Reserved (do not use). FFFFh Table 68. DMA Source Start Address Register − Lower Part (DMACSSAL) Field Descriptions Bits Field...
Page 181: Dma Destination Start Address Register − Upper Part (Dmacdsau) Field Descriptions
DSP DMA Figure 88. DMA Destination Start Address Registers (DMACDSAU and DMACDSAL) DMACDSAU DSAU RW-x DMACDSAL DSAL RW-x Note: R = Read; W = Write; −n = Value after reset; −x = Value after DSP reset is not defined. Table 69. DMA Destination Start Address Register − Upper Part (DMACDSAU) Field Descriptions Bits Field...
Page 182: Dma Element Number Register (Dmacen) And Frame Number
DSP DMA Figure 89. DMA Element Number Register (DMACEN) and Frame Number Register (DMACFN) DMACEN ELEMENTNUM RW-x DMACFN FRAMENUM RW-x Note: R = Read; W = Write; −n = Value after reset; −x = Value after DSP reset is not defined. Table 71.
Page 183 DSP DMA When DINDXMD = 0 (the default forced by a DSP subsystem reset), a compatibility mode is selected. In the original DMA controller design, the source and the destination shared one element index register called DMACEI and one frame index register called DMACFI. When DINDXMD = 0, compatible behavior is enabled;...
Page 184 DSP DMA Valid values for the element index are: [4 x N] + 1 (where N = ...−2, −1, 0, 1, 2...) if the data type is 32-bit [2 x N] + 1 (where N = ...−2, −1, 0, 1, 2...) if the data type is 16-bit Any value if the data type is 8-bit As with the element index, the frame index must produce an aligned address according to the data type selected in the DATATYPE field of DMACSDP.
Page 185: Dma Source Element Index Registers (Dmacsei, Dmacdei) And Frame
DSP DMA Figure 90. DMA Source Element Index Registers (DMACSEI, DMACDEI) and Frame Index Registers (DMACSFI, DMACDFI) DMACEI/DMACSEI ELEMENTNDX RW-x DMACFI/DMACSFI FRAMENDX RW-x DMACDEI ELEMENTNDX RW-x DMACDFI FRAMENDX RW-x Note: R = Read; W = Write; −n = Value after reset; −x = Value after DSP reset is not defined. Table 73.
Page 186: Dma Source Address Counter (Dmacsac) And Destination Address
DSP DMA Table 75. DMA Destination Element Index Register (DMACDEI) Field Descriptions Bits Field Value Description 15−0 ELEMENTNDX −32768 When DINDXMD = 1, DMACDEI contains the destination element to 32767 index (in bytes). Table 76. DMA Destination Frame Index Register (DMACDFI) Field Descriptions Bits Field Value...
Page 187: Ti Peripheral Bus Bridges
Byte access to I/O space is not supported. DSP Private Peripherals Peripherals on the DSP private peripheral bus are considered private peripherals. The MPU cannot access these peripherals. DSP private peripherals on OMAP5910 and OMAP5912 include: Three timers Watchdog timer Interrupt handlers...
Page 188: Dsp Public Peripherals
These peripherals are directly accessible by the DSP core and DSP DMA. The MPU core can also access these peripherals through the MPUI port (see section 9). DSP public peripherals on OMAP5910 and OMAP5912 include: Two Multichannel Buffered Serial Ports (McBSP1 and McBSP3)
Page 189: Tipb Access Rates
Each access factor field in the control mode register controls the access rate for a group of peripherals. Table 80 and Table 81 show the peripherals that are affected by the ACCESS_FACTOR0 and ACCESS_FACTOR1 bits for OMAP5912 and OMAP5910, respectively. SPRU890A DSP Subsystem...
Page 190: Peripherals Affected By Access Factor Bits (Omap5912)
GPIO Mailbox DSP MPUI register ACCESS_FACTOR1 TIPB switch GP timers (x8) 32-KHz synchronization timer MMCSDIO2 GPIO (x4) Table 81. Peripherals Affected by Access Factor Bits (OMAP5910) Access Factor Bits Peripherals Affected TIPB registers ACCESS FACTOR0 ACCESS_FACTOR0 CLKM2 registers UART3 McBSP1...
Page 191: Tipb Control Mode Register (Cmr)
0xE100 control the TIPB bridge module. 0000 † DSP I/O and MPU byte addresses apply to both OMAP5910 and OMAP5912. 8.7.2 TIPB Control Mode Register (CMR) The control mode register (CMR) indicates the access mode of the MPUI and the bus error condition status for accesses to the TIPB bridge module. It also controls DSP core priority versus the MPUI and DSP DMA controller for accesses to peripherals on the DSP public peripheral bus.
Page 192: Tipb Control Mode Register (Cmr) Field Descriptions
TI Peripheral Bus Bridges Figure 92. TIPB Control Mode Register (CMR) DSP Side TIMEOUT ACCESS_ FACTOR1 RW-0x7F RW-1 ACCESS_FACTOR1 ACCESS_FACTOR0 CPU_ BUS_ MPUI_ PRIORITY ERROR MODE RW-1 RW-1 RW-1 MPU Side Reserved TIMEOUT ACCESS_ FACTOR1 R-0x7F ACCESS_FACTOR1 ACCESS_FACTOR0 CPU_ BUS_ MPUI_ PRIORITY ERROR...
Page 193 TI Peripheral Bus Bridges Table 83. TIPB Control Mode Register (CMR) Field Descriptions (Continued) Bits Field Value Description 5−3 ACCESS_ 0−7 These bits set the number of wait states inserted when communicating FACTOR0 with peripherals as listed in Table 80 and Table 81. CPU_PRIORITY This bit determines the priority of the DSP core, MPUI, and DSP DMA controller in the case of simultaneous accesses to the TIPB bridge.
Page 194: Mpu Interface Port
This section is intended to give a brief introduction of the communication between the MPUI port and the MPUI. For additional information, see the OMAP5910 Dual-Core Processor MPU Subsystems Reference Guide (SPRU671) or the OMAP5912 Multimedia Processor OMAP3.2 Subsystem Reference Guide (SPRU749).
Page 195: Mpui Port Modes
MPU Interface Port For complete information on these registers, see the OMAP5910 Dual-Core Processor MPU Subsystems Reference Guide (SPRU671) and the OMAP5912 Multimedia Processor OMAP3.2 Subsystem Reference Guide (SPRU749). 9.2.1 MPUI Port Modes The MPUI port supports two access modes for the DSP subsystem internal memory: Shared-access mode for internal memory (SAM_M).
Page 196: Hom/Sam Change Outside Of Reset
MPU Interface Port 9.2.2 HOM/SAM Change Outside of Reset Only the DSP core can invoke a change between the host-only and shared-access modes outside of reset. OMAP devices use two bits in the DSP core’s ST3_55 register to change between SAM_M and HOM_M and between SAM_P and HOM_P: the HOM_R bit (bit 9) and the HOM_P bit (bit 8), respectively (see Figure 93 and Table 84).
Page 197: Little-Endian Versus Big-Endian Data Format
DSP Subsystem Endianess MPU Interface Port / DSP Subsystem Endianess Table 84. HOM_R and HOM_P Bits in DSP Core Register ST3_55 Bits Field Value Description HOM_R Memory access mode bit. This bit determines whether the MPUI port operates in SAM_M or HOM_M. SAM_M.
Page 198: Endianess Conversion
DSP Subsystem Endianess 10.2 Endianess Conversion Endianess conversion is not always necessary. Conversion is required when the following two conditions are met: Shared data is accessed using different Endian formats. For example, when the MPU core stores data in memory using Little-Endian format and the DSP core reads the same data using Big-Endian data format.
Page 199: Big-Endian Access Of Little-Endian Data
DSP Subsystem Endianess Table 86. Big-Endian Access of Little-Endian Data 32-bit Value (0x1234 5678) 4 LSBs of stored as Little Single 32-Bit Read Two 16-Bit Read Four 8-Bit Read Endian Byte Address Access Accesses Accesses XX00b 0x78 0x1234 5678 0x5678 0x78 XX01b 0x56...
Page 200: Effect Of Dsp Mmu Endianess Conversion Settings
DSP Subsystem Endianess 10.3.1 Endianess Conversion by the DSP MMU Endianess conversion is performed at the boundary between the DSP subsystem and the DSP MMU. The endianess conversion unit of the DSP MMU splits data accesses into individual bytes and reorders them according to the access type and chosen configuration.
Page 201: Endianess Conversion By The Mpui
DSP Subsystem Endianess Figure 94. DSP MMU Endianess Control Register (DSP_ENDIAN_CONV) Reserved Reserved SWAP RW-0 RW-0 Note: R = Read, W = Write; −n = Value after reset; −x = Value after reset is not defined. Table 88. DSP MMU Endianess Control Register (DSP_ENDIAN_CONV) Field Descriptions Bits Field...
Page 202: Effect Of Mpui Endianess Conversion Settings
DSP Subsystem Endianess The endianess conversion unit of the MPUI is configured by the MPU core through the MPUI control register (see section 10.3.2.1). This register contains two configuration bit fields that control the way the endianess conversion is handled: The WORD_SWAP bit field determines whether word swapping is performed on accesses to DSP subsystem internal memory, shared peripherals, or both.
Page 203: Mpui Control Register (Ctrl_Reg)
DSP Subsystem Endianess Figure 95. MPUI Control Register (CTRL_REG) WORD BYTE SWAP SWAP RW-0 RW-3 Note: R = Read, W = Write; −n = Value after reset; −x = Value after reset is not defined. Table 90. MPUI Control Register (CTRL_REG) Field Descriptions Bits Field Value Description...
Page 204: Dsp Subsystem Interrupts
DSP subsystem. For more details on DSP subsystem interrupts, see the OMAP5912 Multimedia Processor Interrupts Reference Guide (SPRU757) or the OMAP5910 Multimedia Processor DSP Subsystem Interrupts Reference Guide (SPRU923). 11.1...
Page 205: Omap5910 Dsp Subsystem Interrupts
DSP Subsystem Interrupts OMAP5910 contains two interrupt controllers for the DSP subsystem: One DSP level 2 interrupt controller (referred to as DSP interrupt level 2) that can handle 16 interrupts. One DSP level 1 interrupt controller (referred to as DSP interrupt level 1) that can handle 32 interrupts.
Page 206: Omap5912 Dsp Subsystem Interrupts
DSP Subsystem Interrupts Figure 97. OMAP5912 DSP Subsystem Interrupts Level 1 interrupt DSP core controller Level 2 interrupt controller Level 2.1 interrupt controller Note: × − No connection. DSP Subsystem SPRU890A...
Page 207: First Level Interrupts
11.2.1 OMAP5910 First Level Interrupt Mapping and Interrupt Registers Table 91 shows the level 1 interrupts sorted by interrupt vector number for OMAP5910. Figure 98 and Figure 99 show the bit layout for the IFR0/IER0 and IFR1/IER1 registers, respectively. SPRU890A...
Page 208: Omap5910 Level 1 Interrupt Mapping
DSP Subsystem Interrupts Table 91. OMAP5910 Level 1 Interrupt Mapping Hardware C55x DSP Vector Interrupt Core Vector Address Priority Name (Byte Address) Name Interrupt Source RESETIV (IV0) IVPD:00h RESET DSP reset (hardware or software) interrupt † NMIIV (IV1) IVPD:08h /SINT1...
Page 209: Ifr0 And Ier0 Bit Locations (Omap5910)
DSP Subsystem Interrupts Table 91. OMAP5910 Level 1 Interrupt Mapping (Continued) Hardware C55x DSP Vector Interrupt Core Vector Address Priority Name (Byte Address) Name Interrupt Source IV18 IVPH:90h DMAC0 DSP DMA channel #0 interrupt IV19 IVPH:98h MBX2 MPU-to-DSP mailbox #2...
Page 210: Ifr1 And Ier1 Bit Locations (Omap5910)
DSP Subsystem Interrupts Figure 99. IFR1 and IER1 Bit Locations (OMAP5910) Reserved RTOS DLOG BERR RW-0 RW-0 RW-0 TIMER1 TIMER2 DMAC3 DMAC2 MBX2 DMAC0 LCLBUS EMIF RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
Page 211 DSP Subsystem Interrupts Table 92. OMAP5912 Level 1 Interrupt Mapping (Continued) Hardware C55x DSP Vector Interrupt Core Vector Address Priority Name (Byte Address) Name Interrupt Source IVPD:40h TIMER3 DSP private timer #3 interrupt IVPD:48h DMAC1 DSP DMA channel #1 interrupt IV10 IVPD:50h MPU interrupt to DSP...
Page 212: Ifr0 And Ier0 Bit Locations (Omap5912)
DSP Subsystem Interrupts Table 92. OMAP5912 Level 1 Interrupt Mapping (Continued) Hardware C55x DSP Vector Interrupt Core Vector Address Priority Name (Byte Address) Name Interrupt Source RTOSIV (IV26) IVPD:D0h RTOS Real-time operating system interrupt SIV27 IVPD:D8h SINT27 Software interrupt #27 SIV28 IVPD:E0h SINT28...
Page 213: Omap5910 Level 2 Interrupt Mapping
For each interrupt, you must specify whether the interrupt is edge or level sensitive. On OMAP5910, the level 2 interrupt handler generates a single interrupt to INT3 on the level 1 interrupt handler. The level 2.0 interrupt handler on OMAP5912 generates a single interrupt to INT3 on the level 1 interrupt handler, while level 2.1 generates a single interrupt to INT17.
Page 214: Omap5912 Level 2.0 Interrupt Mapping
DSP Subsystem Interrupts Table 94. OMAP5912 Level 2.0 Interrupt Mapping Required Level 2 Sensitivity Mapping Name Setup Function IRQ_0 MCBSP3_TX Level McBSP #3 transmit interrupt IRQ_1 MCBSP3_RX Level McBSP #3 receive interrupt IRQ_2 MCBSP1_TX Level McBSP #1 transmit interrupt IRQ_3 MCBSP1_RX Level McBSP #1 receive interrupt...
Page 215 DSP Subsystem Interrupts Table 95. OMAP5912 Level 2.1 Interrupt Mapping (Continued) Required Level 2 Sensitivity Mapping Name Setup Function IRQ_5 GPTIMER5 Level General purpose timer #5 interrupt IRQ_6 GPTIMER6 Level General purpose timer #6 interrupt IRQ_7 GPTIMER7 Level General purpose timer #7 interrupt IRQ_8 GPTIMER8 Level...
Page 216: Dsp Subsystem Reset, Clocking, Idle Control, And Boot
Multimedia Processor Initialization Reference Guide (SPRU752). 12.1.1 Hardware (Cold) Resets OMAP5912 and OMAP5910 devices have external pins which can be used to generate hardware resets. On the OMAP5910/5912 devices, these pins include PWRON_RESET and MPU_RST, The OMAP5912 device also has the RTC_ON_NOFF pin.
Page 217: Omap Clock Generation
DSP external DSPXOR_CK peripherals The DSP clock generator on both OMAP5910 and OMAP5912 provides two clocks which affect most of the modules described in this reference guide: the DSP subsystem master clock and the DSP MMU clock (see Figure 104).
Page 218: Generation Of Dsp Subsystem Master Clock And Dsp Mmu Clock
For more information on OMAP clock architecture and control, see the following documents: OMAP5912 Multimedia Processor Clocks Reference Guide (SPRU751), the OMAP5912 Multimedia Processor OMAP3.2 Subsystem Reference Guide (SPRU749), and the OMAP5910 Dual-Core Processor Clock Generation and System Reset Management Reference Guide (SPRU678).
Page 219: Idle Domains In The Dsp
MPU Clock Control Prescaler Selection Register to (ARM_CKCTL). For more information on the ARM_RSTCT1 and ARM_CKCTL registers, see the OMAP5912 Multimedia Processor OMAP3.2 Subsystem Reference Guide (SPRU749), or the OMAP5910 Dual-Core Processor Clock Generation and System Reset Management Reference Guide (SPRU678). 12.3.2 Idle Control at the DSP Module Level The DSP module is divided into the idle domains described in this section.
Page 220 DSP Subsystem Reset, Clocking, Idle Control, and Boot Table 96. Idle Domains in the DSP (Continued) Domain Contents of the Domain Configurability CACHE Instruction cache When the IDLE instruction is executed, the instruction cache remains active or becomes idle, depending on the chosen idle configuration.
Page 221: Idle Configuration Process
DSP Subsystem Reset, Clocking, Idle Control, and Boot Figure 105. Idle Configuration Process Idle configuration register (ICR) Copy initiated by IDLE instruction Idle status register (ISTR) EMIF CACHE domain domain domain domain 12.3.2.3 Valid Idle Configurations Not all of the values that you can write to the idle configuration register (ICR) provide valid idle configurations.
Page 222: Changing Idle Configurations
DSP Subsystem Reset, Clocking, Idle Control, and Boot Table 97. Changing Idle Configurations Available Methods For Changing Idle Configuration Condition ISTR After Change ICR After Change 1. CPU domain A. Write a new configuration to the A. Modified by the IDLE A.
Page 223: Dsp Core Response After Reactivation
DSP Subsystem Reset, Clocking, Idle Control, and Boot 12.3.2.5 Interrupt Handling When the DSP Core Is Reactivated If the DSP core has been halted by an idle configuration, it can be reactivated by a DSP subsystem reset or by a maskable interrupt that is enabled in an interrupt enable register (IER0 or IER1).
Page 224: Placing The Dsp Dma In Idle
DSP Subsystem Reset, Clocking, Idle Control, and Boot Placing the DSP DMA in Idle To set the DSP DMA domain to idle, follow these steps: 1) Set the DMA domain bit in the idle control register (ICR) by writing 0x0002 to ICR.
Page 225: Idle Control Register (Icr)
0x0002 the idle domains. † DSP I/O addresses apply to both OMAP5910 and OMAP5912. ICR lets you configure how each idle domain will respond upon IDLE instruction execution. When you execute the IDLE instruction, the content of ICR is copied to ISTR. The ISTR values are then propagated to the idle domains.
Page 226: Idle Status Register (Istr)
DSP Subsystem Reset, Clocking, Idle Control, and Boot Table 100. Idle Control Register (ICR) Field Descriptions Bits Field Value Description 15−6 Reserved − These bits are read-only and return 0s when read. EMIFI EMIF-domain idle configuration bit. EMIFI determines whether the external memory interface (EMIF) will be idle after the next execution of the IDLE instruction: EMIF will be active.
Page 227: Idle Status Register (Istr) Field Descriptions
DSP Subsystem Reset, Clocking, Idle Control, and Boot Table 101. Idle Status Register (ISTR) Field Descriptions Bits Field Value Description 15−6 Reserved − These bits are not available for your use. They are read-only bits and return 0s when read. EMIFIS EMIF-domain idle status bit.
Page 228: Dsp Bootloader
DSP Bootloader 12.4.1 Introduction This section provides a description of the features of the on-chip DSP bootloader provided with the OMAP5910 and OMAP5912 devices. 12.4.1.1 Bootloader Features OMAP devices contain program code residing in the DSP subsystem PDROM, called a bootloader. The bootloader is executed by the DSP core when it is taken out of reset.
Page 229: Dsp Pdrom Contents
DSP Subsystem Reset, Clocking, Idle Control, and Boot Table 102. DSP PDROM Contents Starting Byte Address Contents 0xFF_8000 DSP Bootloader 0xFF_8200 Reserved 0xFF_FF00 Interrupt Vector Table 12.4.2 Bootloader Operation The following sections describe the structure and operation of the bootloader. 12.4.2.1 Bootloader Initialization When the bootloader begins execution, it performs some initialization of DSP...
Page 230: Dsp Boot Configuration Register (Dsp_Boot_Config)
DSP Subsystem Reset, Clocking, Idle Control, and Boot 12.4.2.2 Boot Mode Selection The bootloader mode (or boot mode) used by the bootloader is specified by core using Boot Configuration Register (DSP_BOOT_CONFIG). This register is read-only for the DSP and is mapped to address 0x000F in the DSP I/O space (within the DSP TIPB address space).
Page 231: Registers For Dsp Module Idle Control
DSP Subsystem Reset, Clocking, Idle Control, and Boot Note: The DSP MMU will determine the actual physical location of the PDROM memory space when the on-chip PDROM is disabled. Table 105 lists the supported boot modes. Table 105. Registers for DSP Module Idle Control BOOT_MODE[3:0] Boot Process Description...
Page 232 DSP Subsystem Reset, Clocking, Idle Control, and Boot 12.4.3.2 External Memory Boot Mode When BOOT_MODE[3:0] = 0001b, the External Memory Boot mode is selected. In this mode, the bootloader does execute. After initializing the resources described in section 12.4.2.1, the bootloader simply branches to byte address 0x08 0000 in DSP external memory.
Page 233: Bootloader Sequence
DSP Subsystem Reset, Clocking, Idle Control, and Boot If the application has been previously loaded and another external reset is necessary (warm boot), the MPU core can reset the DSP subsystem without reloading the application code, and the application execution will begin. 12.4.4 Bootloader Sequence The next two sections describe the entire bootloader sequence for all of the...
Page 234: Document Revision History
Revision History Table 106 lists the changes made since the previous version of this document. Table 106. Document Revision History Page Additions/Modifications/Deletions Updated the byte address for the external memory space to 0x02 8000 in section 3.2. Deleted reserved row, and changed the byte address for the external memory space to 0x02 8000−0xFF 7FFF, and the word address to 0x01 4000−0x7F BFFF.

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Texas Instruments OMAP5910 Reference Manual

Digital Signal Processor Subsystem Overview

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DSP Subsystem Memory

Instruction Cache

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DSP Memory Management Unit

TI Peripheral Bus Bridges

MPU Interface Port

DSP Subsystem Endianess

DSP Subsystem Interrupts

DSP Subsystem Reset, Clocking, Idle Control, and Boot

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