Dma Operation - Texas Instruments OMAP5910 Technical Reference Manual

MMC/SD Host Controller

7.12.9 DMA Operation

7.12.9.1 MMC DMA Receive Mode
7-166
In a DMA block read operation (single or multiple):
-
The DMA RX request signal is asserted to its active level when the FIFO
level becomes equal or greater than the threshold set in AF_level.
-
The DMA RX request is deasserted to its inactive level when the system
DMA has read one word from the FIFO.
Because the request lasts one 16-bit word read cycle, it is recommended that
the threshold level (AF_level) equal the DMA burst size (n) minus 1. For
instance, if the system DMA is programmed to support one word read access,
AF_level must be set to 0.
The MMC/SD host controller does not generate a new DMA request until the
system DMA has read the N words corresponding to the previous DMA
request, even if the FIFO level is equal to or greater than the programmed
threshold.
Since each DMA transfer has equal size, it is necessary to have the total data
size of the transfer be a multiple of the DMA read access size (max 32 words).
Summary:
DMA transfer size = n ≤ FIFO size
(max 32 16-bit words)
AF_level = n -1 (FIFO threshold level)
n = submultiple of total transfer size
Example: Multiple block read of 10 blocks of 512 bytes each.
The DMA transfer size n can be set to 20 words (40 bytes) and AF_
level= 0x13 (0x14-1). Then the read transfer operation completes
after 128 system DMA read requests.
The receive FIFO does not overflow. If the FIFO gets full, the MMC_clk clock
signal is momentarily stopped until the system DMA or the TI925T performs
a read access, which starts emptying the FIFO.
When using the MMC DMA receive mode, the MPU software must enforce that
the MPU never access the MMC_DAT register at the same time the DMA
is accessing the register. Failure to enforce this restriction may cause
unexpected results.