Mmu Translation Process; Translation Look-Aside Buffer (Tlb) - Texas Instruments OMAP5910 Reference Manual

Figure 25.

MMU Translation Process

Translation request
Translation
in TLB
No
(Miss)
Table
walking
enabled
No
Translation
fault
6.2.2

Translation Look-Aside Buffer (TLB)

SPRU890A
Yes
Retrieve
translation
(Hit)
?
Read
Yes translation
tables and
retrieve
?
descriptor
To increase the virtual-to-physical address translation process speed, a cache
mechanism (the TLB) is introduced to store the results of recent translations.
For every translation request, the MMU internal logic checks first whether this
translation already exists in the TLB. If the translation is in the TLB (a TLB hit),
then this translation is used. If the address translation is not in the TLB (a TLB
miss), the table walking logic (described in section 6.2.3) retrieves the address
translation from the translation tables and updates the TLB. If the table walking
logic is disabled, a translation fault is generated and the MPU core is
interrupted.
Entries in the TLB are replaced, or evicted, by the table walking logic when the
TLB is full. The table walking logic selects the entry to be replaced at random.
DSP Memory Management Unit
Send memory
request to
traffic
controller
Yes
Access
No
permissions
correct
?
Update
TLB
Yes
Descriptors
valid
?
No
Permission
fault
DSP Subsystem 69