Memory Interfaces - Texas Instruments OMAP5910 Reference Manual

Memory Interfaces

Table 3. MPU Memory Map (Continued)
Device Name
MPU Private TIPB Peripherals (Strobe 1) (Continued)
MPU Timer 3
MPU watchdog timer
MPUI
MPU private TIPB bridge
MPU level 1 interrupt handler
Traffic controller
Reserved
MPU CLKM (clock control)
DPLL1
Reserved
Reserved
DSP MMU
MPU public TIPB bridge
JTAG ID code
Reserved
System DMA controller
Reserved
†
Each register must always be accessed using the appropriate data access width as indicated in this table. Failure to do so
may result in unexpected behavior including a TIPB bus error condition with an associated interrupt. Reserved address loca-
tions should never be accessed.
3 Memory Interfaces
20 Memory Interface Traffic Controller
Start Address
FFFE:C700
FFFE:C800
FFFE:C900
FFFE:CA00
FFFE:CB00
FFFE:CC00
FFFE:CD00
FFFE:CE00
FFFE:CF00
FFFE:D000
FFFE:D100
FFFE:D200
FFFE:D300
FFFE:D400
FFFE:D500
FFFE:D800
FFFE:E000
The TC has three memory interfaces:
Internal memory interface (IMIF)
-
External memory interface slow (EMIFS)
-
External memory interface fast (EMIFF)
-
End Address Size in Bytes
FFFE:C7FF 256 bytes
FFFE:C8FF 256 bytes
FFFE:C9FF 256 bytes
FFFE:CAFF 256 bytes
FFFE:CBFF 256 bytes
FFFE:CCFF 256 bytes
FFFE:CDFF 256 bytes
FFFE:CEFF 256 bytes
FFFE:CFFF 256 bytes
FFFE:D0FF 256 bytes
FFFE:D1FF 256 bytes
FFFE:D2FF 256 bytes
FFFE:D3FF 256 bytes
FFFE:D4FF 256 bytes
FFFE:D7FF
FFFE:DFFF 2K bytes
FFFE:FFFF 2K bytes each
†
Data Access
32 R/W
32 R/W
32 R/W
32 R/W
32 R/W
32 R/W
32 R/W
32 R/W
32 R/W
16 R/W
32 R/W
16 R/W
SPRU673