Emif Global Control Register (Emif Gcr) - Texas Instruments OMAP5910 Technical Reference Manual

EMIF
3.7 EMIF
3.7.1 EMIF Global Control Register (EMIF_GCR)
Table 3–11. EMIF Global Control Register (EMIF GCR)
Bit Name
15–12 Reserved
11–8 Reserved
7 WPE
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Reserved
3-36
The external memory interface (EMIF) is a DSP subsystem module that gives
the DSP access to the shared system memory managed by the traffic control-
ler. The EMIF interfaces directly to a 32-bit wide system bus. This bus can
operate at the CPU clock rate with sustained throughput during burst
accesses. The EMIF has two control registers for user configuration:
-
EMIF global control register (GCR)
-
EMIF global reset register (GRR)
The EMIF global control register (GCR) configures general operation of the
EMIF module. The EMIF GCR appears at word address 0x0800 in the DSP
I/O space.
Function
Write posting enable
WPE=0, write posting is disabled (for debug).
WPE=1, write posting is enabled.
Reset
Type Value
R 0
RW 0
RW 0
RW 0
RW 1
R 0
R x
R x
R 0
RW 0