Emifs Operation - Texas Instruments OMAP5910 Reference Manual

Memory Interfaces
3.2.2

EMIFS Operation

24 Memory Interface Traffic Controller
The low-priority queue order is:
J
H MPU
H DSP
Local bus
H
H DMA (all channels excluding LCD)
The high-priority queue order is:
J
H DSP
H Local bus
H DMA transfer involving channels other than LCD channel
Fixed priority is a special case of dynamic priority. To create a fixed priority,
-
all time-out registers must have a value of 0. This way any request made
goes into the high-priority queue after one clock cycle. Then the high-
priority queue provides a fixed priority.
This interface generates the appropriate signal timings to drive the following
types of devices or compatible devices:
Intel fast boot block flash (23FxxxF3)
-
AMD simultaneous read/write boot sector flash (AM29DLxxxG)
-
AMD burst mode flash (AM29BLxxxC)
-
Intel StrataFlash memory (28FxxxJ3A)
-
Intel synchronous StrataFlash memory (28FxxxK3/K18)
-
Intel wireless flash memory (28FxxxW18)
-
Asynchronous SRAM
-
Every flash command (read array, program, clear status register) is sent to the
flash memory controller by the MPU. The MPU writes in the flash, followed by
a read or a write, to set up the flash in the correct mode.
File/boot block flash basic operations supported are:
Asynchronous read, including specific reads like manufacturer ID
-
Burst read emulation (by multiple asynchronous reads) in 32-bit width
-
Reset or power down
-
Asynchronous write with WE in 16-bit width
-
The following operations are also supported for burst flash devices:
Synchronous burst read mode (for Intel and AMD flashes)
-
An additional read mode is provided that supports burst read on page mode
ROM devices.
Figure 3 through Figure 7 show the external timing of the protocols used by
the EMIF slow interface.
SPRU673