I-Cache Global Control Register (Gcr) - Texas Instruments OMAP5910 Reference Manual

4.6.2

I-Cache Global Control Register (GCR)

Figure 12. I-Cache Global Control Register (GCR)
15 14
CUT_ AUTO_
CLOCK GATING
RW-1 RW-1
7
HLFRAMSET_
NUMR
RW-00
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined
SPRU890A
Before enabling the I-Cache (by setting CAEN = 1), use the global control
register (GCR) to select from the different cache options.
Note that n
ot all functions described in the GCR are supported on OMAP5912
and OMAP5910. For example, the I-Cache supports the 2-way option for the
N-way cache and zero, one, or two RAM sets. The following bits must be set
as specified:
CUT_CLOCK = 1
-
AUTO_GATING = 1
-
FLUSH_LINE = 0; line flushing is not supported, instead the entire cache
-
must be flushed as a whole.
GLOBAL_FLUSH = 1; flushing individual portions of the cache is not
-
supported.
WAY_NUMR = X1b; only 2-way cache is supported.
-
GLOBAL_ENABLE = 1; enabling individual portions of the cache
-
separately is not supported, instead the entire cache must be enabled as
a whole.
13 12
FLUSH_
Reserved
LINE
RW-0 RW-0
5 4
WAY_NUMR
11 10
HLFRAM-
GLOBAL_
SET_
FLUSH
PRESENCE
RW-0 RW-0
3 2
STREAM-
ING
RW-00 RW-1
Instruction Cache
9 8
HLFRAM-
WAY_
SET_
PRESENCE
NUMR
RW-0 RW-00
1 0
RAM_FILL_ GLOBAL_
MODE ENABLE
RW-1 RW-0
DSP Subsystem 49