Timer Registers - Texas Instruments OMAP5910 Technical Reference Manual

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Timers
8.2.4

Timer Registers

Table 8–4. Timer Registers
Register Name
CNTL_TIMER
LOAD_TIM_HI
LOAD_TIM_LO
READ_TIM
TIMER_MODE
Table 8–5. Control Timer Register (CNTL_TIMER)
Bit
Name
15–8
Unused
7
SOFT
6
FREE
5
CLOCK_ENABLE
4–2
PTV
1
AR
8-6
Table 8–4 lists the timer registers. Table 8–5 through Table 8–12 describe the
register bits.
Description
R/W
Control timer
R/W
Load timer—high
Load timer—low
Read timer
Timer mode
R/W
Value
Descriptions
This bit is used with the FREE bit to determine peripheral
state when a breakpoint is encountered. Used in emulation
mode.
0
Peripheral halts immediately, either retaining or discarding
current state.
1
Peripheral stops after completion of current task.
This bit is used with the SOFT bit to determine peripheral
state when a breakpoint is encountered. Used in emulation
mode.
0
SOFT bit selects emulation mode.
1
Peripheral clock runs free regardless of the SOFT bit.
External timer clock enable
Prescale clock timer value
0
0: One-shot timer
1
Autoreload timer
Size (Bits)
16
W
16
W
16
R
16
16
Offset
Reset Value
0x00
0x0002
0x02
0xFFFF
0x03
0xFFFF
0x02
0xFFFF
0x04
0x8000
Reset
Value
0
0
0
0
0

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