Idle Configuration Register (Icr); Idle Status Register (Istr) - Texas Instruments OMAP5910 Technical Reference Manual

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Table 3–9. Idle Configuration Register (ICR)
ICR [15–0]
Description
15–8
Reserved (not connected)
7
Reserved idle domain
6
Reserved idle domain
5
EMIF idle domain
4
DPLL idle domain
3
Peripherals idle domain
2
Cache idle domain
1
DMA idle domain
0
CPU idle domain
Note:
When the DSP subsystem comes out of IDLE, the ICR configuration is retained until modified by the CPU. The next
time an IDLE instruction is executed, the same domains enter the idle state.
Table 3–10. Idle Status Register (ISTR)
ISTR[15–0]
Description
15–8
Not connected
7
Reserved idle status
6
Reserved idle status
5
EMIF idle status
4
DPLL idle status
3
Peripherals idle status
2
Cache idle status
1
DMA idle status
0
CPU idle status
3-32
DSP Access
MPU Access
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
DSP Access
MPU Access
Read
Read
Read
Read
Read
Read
Read
Read
Read
Reset Value
Read
0x0
Read
0
Read
0
Read
0
Read
0
Read
0
Read
0
Read
0
Read
0
Reset Value
Read
0x0
Read
0
Read
0
Read
0
Read
0
Read
0
Read
0
Read
0
Read
0

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