Sdram Read Single 16-Bit Half-Word Followed By Read Burst 8 Half-Word - Texas Instruments OMAP5910 Reference Manual

Dual-core processor memory interface traffic controller
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Figure 12.

SDRAM Read Single 16-Bit Half-Word Followed by Read Burst 8 Half-Word

ACCESS_REG
2
ACCESS_GRANT
COMMAND
ADDRESS
DQ
CURRENT_COL
CURRENT_SIZE
DVALID
SAVE_ADD
LAST_DATE
READ (burst reduced to 1) is followed by a READ burst (8) in a different bank and in a page already active.
Note:
SPRU673
ACTV0
READ
READ
2
B0/R0
B0/C0
B1/C1
C0+1 C1+1
C0
C1
C1+1
0
7
L = 3
Q
Q
Q
Q
C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 C1+8
C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
6
5
4
3
2
Memory Interface Traffic Controller
Memory Interfaces
STOP
Q
Q
Q
Q
Q
Output column counter
1
0
43

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