32-Bit Timer; Timer Level 1 Interrupt; Timer Description - Texas Instruments OMAP5910 Technical Reference Manual

6.2 Timer Description

Figure 6–2. 32-Bit Timer
MPUTIM_CK
12 MHz
Table 6–1. Timer Level 1 Interrupt
Three 32-bit timers for the operating system provide general-purpose house-
keeping functions. These timers are configured either in autoreload or one-
shot mode with on-the-fly read capability. The timers generate an interrupt to
the TI925T RISC processor when equal to zero. Figure 6–2 shows the 32-bit
timer.

32-bit timer

CLK
Divide clock down by
2 (PTV+1)
Table 6–1 identifies the level 1 interrupts for the three 32-bit timers.
Timer
1
2
3
The timers are 32-bit counters that receive a dedicated clock from clock gener-
ator module 1 (either CLKIN or DPLL1 output). This clock can then be pres-
caled, which divides it down further. Prescaling is controlled by the PTV field
of the control timer register (CNTL_TIMER) (see Table 6–1).
Load when timer starts
CLK / 2 (PTV+1)
Timer 1: IRQ_26
Timer 2: IRQ_30
Timer 3: IRQ_16
Corresponding Level 1 Interrupt
IRQ_26
IRQ_30
IRQ_16
MPU Private Peripherals
Timer Description
LOAD_TIM
If autoreload, then
load when timer
underflows
READ_TIM
IRQ when timer
underflows
6-3