Instruction Cache Architecture; Introduction To The I-Cache - Texas Instruments OMAP5910 Reference Manual

Instruction Cache
4.2

Instruction Cache Architecture

4.2.1

Introduction to the I-Cache

4.2.2 Instruction Cache Blocks
4.2.2.1 2-Way Cache
32 DSP Subsystem
When the DSP core requests instructions, it requests 32 bits at a time. To
initiate an instruction fetch, the DSP core sends a fetch request and a fetch
address to the I-Cache.
If the I-Cache is enabled, it handles the fetch request as follows. If the
requested word is in the I-Cache (a hit), the I-Cache delivers the word to the
DSP core. If the requested word is not in the I-Cache (a miss), the I-Cache
uses the external memory interface (EMIF) to fetch the 4-word DSP external
memory block that contains the requested word. As soon as the requested
word arrives in the I-Cache, it is delivered to the DSP core. Section 4.2.10
describes timing information for I-Cache hits and misses.
If the I-Cache is disabled, it is not checked. Instead, the fetch request and fetch
address are passed to the EMIF. Once fetched by the EMIF, the requested
32-bit word is passed directly to the DSP core.
Notes:
1) The DSP external memory address generated by the EMIF is a virtual
address. This virtual address is mapped to a physical address within the
memory space of the OMAP device by the DSP Memory Management
Unit (MMU). Before enabling the I-Cache, you must configure the DSP
MMU such that the correct physical address is read during line-fill
operations. Section 6 describes the DSP MMU.
2) The I-Cache does not automatically maintain coherency. If you write to
a location in program memory, the corresponding line in the I-Cache is
not updated. To regain coherency you must flush the I-Cache as
described in section 4.2.4.2.
As shown in Figure 6, the 2-way cache has two memory banks. Each memory
bank includes a:
Data array. Each data array contains 512 lines (0 through 511) that the
-
I-Cache can fill individually in response to misses in the 2-way cache.
Line valid (LV) bit array. Each line has a line valid bit. Once a line has been
-
loaded, its line valid bit is set. Whenever the I-Cache is flushed, all 512 line
valid bits are cleared, invalidating all the lines. For more information on
flushing the I-Cache, see section 4.2.4.2.
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