Supported Cache Configurations; Conceptual Block Diagram Of The I-Cache In The Dsp Subsystem - Texas Instruments OMAP5910 Reference Manual

Figure 5.

Conceptual Block Diagram of the I-Cache in the DSP Subsystem

4.1.3

Supported Cache Configurations

SPRU890A
OMAP device
DSP subsystem
DSP core
Cache control bits in
ST3_55 to enable, freeze,
and flush I-Cache
Data read/write logic
to configure and
monitor I-Cache
Instruction buffer
queue
Internal SRAM
The I-Cache supports the following configurations:
2-way 16KB cache with no RAM set blocks
-
2-way 16KB cache with one 4KB RAM set block
-
2-way 16KB cache with two 4KB RAM set blocks
-
Sections 4.3, 4.4, and 4.5 detail the steps required to implement these cache
configurations.
I-Cache
Control logic
I-Cache registers
Instruction storage
memory banks
2-way cache
RAM set 1
RAM set 2
I-Cache
I-Cache
enabled
disabled
EMIF
DSP MMU
Traffic controller
External memory
DSP Subsystem
Instruction Cache
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