Default Configuration At Reset - Texas Instruments OMAP5910 Technical Reference Manual

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TIPB Registers

Table 7-2. Default Configuration at Reset

3) The camera, the OMAP5910 device camera interface, and the system

DMA continue transfer of data. That is, 352/2 * 288 = 50688 transfers for

a camera interface image format. After the full image is transferred, the

DMA sends an interrupt to the TI925T to signal that the end of frame

There are many ways that the camera interface and system DMA can be

configured to move the data, but in the above sequence the interrupt load on

the TI925T is minimal.

The camera interface contains seven registers for communication between

the TIPB and camera module. They mainly control clock generation, interrupt

request, and status register (see Section 7.2.1.10).

The address of each register is the start address (FFFB:6800) plus the offset

indicated in Table 7-3.

Table 7-2 shows the default configuration of several critical register fields at

reset. See Table 7-4 through Table 7-10 for full descriptions of these register

Interrupts on VSYNC and HSYNC disabled

Division rate for CAM.EXCLK = 1 (12 MHz)

Data latched on rising edge of CAM.LCLK

CAM.EXCLK disabled

Internal clock disabled

DPLL clock source disabled

Trigger level = 1 word

MPU Public Peripherals

Camera Interface