Emifs Priority Handler - Texas Instruments OMAP5910 Reference Manual

Table 4. External Memory Interface Slow Signal List (Continued)
Signal Name
FLASH.A[24:1]
FLASH.BE
†
FLASH.CS2 and FLASH.BAA are multiplexed on the same device pin. Pin function is selected using the OMAP5910 configu-
ration register, FUNC_MUX_CRTL_0. The FLASH.CS2 functionality is default.
3.2.1

EMIFS Priority Handler

SPRU673
I/O Bus Description
O 24 −1 Flash data bus to external device
O 3 −0 External byte enable
Note:
OMAP5910 multiplexes the FLASH.CS2 and FLASH.BAA pin functionality
to the same device pin. Selecting the FLASH.BAA function to enable burst
flash advance acknowledge disables FLASH.CS2 functionality. In this case,
capability of the EMIFS interface is reduced from a maximum of four external
devices to a maximum of three external devices.
This memory interface has two software-selectable priority algorithms for
resolving simultaneous access requests: least recently used and dynamic
priority. The priority scheme is shared with the IMIF and EMIFF and is set in
the OMAP5910
FUNC_MUX_CTRL_0). See Chapter 6, MPU Private Peripherals, for details
on configuration registers.
Least recently used
-
A round-robin arbitration scheme. The highest priority requestor is the
J
one that least recently accessed the memory.
Dynamic priority
-
Dynamic priority uses high- and low-priority queues
J
Each requestor, except the MPU, has a time-out register allocated to it
J
(see Time-Out Registers in Section 4). These registers hold the
number of clock cycles that a low-priority queue request must wait
before it is moved from the low priority queue to the high-priority
queue.
At reset, all requestors are initially in the low-priority queue and the
J
time-out registers are set to minimum value for each requestor. Users
must program these registers before using dynamic priority.
configuration registers
Memory Interface Traffic Controller
Memory Interfaces
(bit 20, LRU_SEL in
23