Mmc/Sd Host Controller Clocks And Reset - Texas Instruments OMAP5910 Technical Reference Manual

MMC/SD Host Controller

7.12.3 MMC/SD Host Controller Clocks and Reset

7.12.4 MMC/SD Host Controller DMA Request
7.12.5 MMC/SD Host Controller Interrupt
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The MMC/SD host controller has two clocks:
-
An interface clock (clock_i) used between the MPU TIPB and the MMC/SD
host controller and connected to the MPU peripheral programmable clock
(PERCLK), is determined dividing CK_GEN1 (the output of DPLL1) by the
value associated with the PERDIV field of the ARM_CKCTL register
(0xFFFECE00).
This clock is a free-running clock when the system is awake.
-
A 48-MHz functional clock (ADP_CLK_I), which is generated by the ULPD
DPLL.
This clock is requested by setting to 1 the CONF_MOD_MMC_SD_CLK_REQ
bit(23) of the MOD_CONF_CTRL_0 register.
The MPU TIPB reset (MPU_PER_RST) resets the MMC/SD host controller.
The MMC/SD host controller can use:
-
Receive DMA channel (DMA_RD_REQ_OQN), which is connected to the
SYSTEM DMA request [21].
-
Transmit DMA channel (DMA_WR_REQ_OQN), which is connected to
the SYSTEM DMA request [20].
See Section 13.1.4 DMA for more details.
The MMC/SD controller can generate one interrupt (IRQ_OQN), which is
connected to the MPU level 2 interrupt handler, line 23 (level-sensitive).