Multichannel/Normal Short Framing/Burst
Figure 9–21. Multichannel/Normal Short Framing/Burst
CLK
FSYNCH
TXD
Channel0
Channel1
Single-Channel/Normal Short Framing
Figure 9–22. Single-Channel/Normal Short Framing
CLK
FSYNCH
TXD
RXD
Single-Channel/Normal Short Framing/Burst
Figure 9–23. Single-Channel/Normal Short Framing/Burst
CLK
FSYNCH
TXD
RXD
Channel14 Channel15
OVER_CLOCK_REG = 0x0013
T7
T6
T5
T4
T3
R7
R6
R5
R4 R3
First frame
T7
T6
T5
T4
T3
R7
R6
R5
R4 R3
T2
T1
T0
T7 T6
R2
R1
R0
R7
R6
T2
T1
T0
R2
R1
R0
DSP Public Peripherals
Multichannel Serial Interfaces
Channel0
Channel1
Channel2
T5
T4
T3
T2
T1
R5
R4 R3
R2
R1
Last frame
T7 T6
T5
T4
T3
R7
R6
R5
R4 R3
T0
R0
T2
R2
9-41