Possible Sdram Configurations - Texas Instruments OMAP5910 Technical Reference Manual

Table 4–7. Possible SDRAM Configurations
Memory Size Bus
(Bytes) Size
64M 2 x 8
32M 1 x 16
2 x 8
16M 1 x 16
2 x 8
8M 1 x 16
4M 2 x 8
2M 1 x 16
The burst length on the SDRAM is variable from 1-8 words and can be 32
words in the case of the LCD controller. The burst length is controlled by the
SDRAM controller depending on how quickly EMIFF requests are received
from the various initiators within the OMAP system (MPU, DSP subsystem,
system DMA, local bus). The actual burst length is not controlled with the burst
size of the SDRAM MRS configuration register, which must always be set with
continuous burst. Depending on the system loading within the device and the
specific configurations and interactions between the different initiators, burst
transfers may or may not be achieved on the EMIFF by any specific initiator.
However, the SDRAM request management logic within the SDRAM controller
allows only bursts of 8 words, except for the LCD refresh channel which can
achieve a burst of 32 words.
The SDRAM controller supports:
-
The self-refresh mode (idle) and autorefresh (normal operation)
-
Automatic generation of MRS and EMRS commands to the SDRAM by
writing to a mirror configuration register within the OMAP5910 device
-
Burst sizes of 1x8, 1x16, 1x32, and 4x32 for all accesses and 8x16 burst
access for LCD.
-
Burst across page boundary (local address increment coupled with
current address register)
-
Two pipelined levels of request from the SDRAM request manager to
enable page interleave timing and reduce overhead cycles by the burst
interruption mechanism
Number of
Devices Type of Device
2 256M bytes organized in 32M x 8
1 256M bytes organized in 16M x 16
2 128M bytes organized in 16M x 8
1 128M bytes organized in 8M x 16
2 64M bytes organized in 8M x 8
1 64M bytes organized in 4M x 16
2 16M bytes organized in 2M x 8
1 16M bytes organized in 1M x 16
Memory Interface Traffic Controller
Memory Interfaces
4-27