Dma Global Timeout Control Register (Dmagtcr) Field Descriptions; Dma Channel Control Register (Dmaccr) - Texas Instruments OMAP5910 Reference Manual

DSP DMA
Table 62. DMA Global Timeout Control Register (DMAGTCR) Field Descriptions
Bits Field
15−2 Reserved
1 DTCE
0 STCE
7.3.5

DMA Channel Control Register (DMACCR)

164 DSP Subsystem
Value Description
These read-only bits return 0s when read.
DARAM timeout counter enable bit. This bit enables/disables the
timeout counter used to monitor delays on DMA requests to the
DARAM port.
0 DARAM timeout counter disabled.
1 DARAM timeout counter enabled.
SARAM timeout counter enable bit. This bit enables/disables the
timeout counter used to monitor delays on DMA requests to the
SARAM port.
0 SARAM timeout counter disabled.
1 SARAM timeout counter enabled.
Each channel has a channel control register as shown in Figure 84. This
I/O-mapped register enables you to:
Choose how the source and destination addresses are updated
-
(SRCAMODE and DSTAMODE)
Enable and control repeated DMA transfers (AUTOINIT, REPEAT, and
-
ENDPROG)
Enable or disable the channel (EN)
-
Choose a low or high priority level for the channel (PRIO)
-
Select element synchronization or frame synchronization (FS)
-
Determine what synchronization event (if any) initiates a transfer in the
-
channel (SYNC)
Table 63 describes the register fields.
SPRU890A