Mmc System Configuration Register (Mmc_Con) - Texas Instruments OMAP5910 Technical Reference Manual

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Table 7–98. MMC System Configuration Register (MMC_CON)

Bus Width During Data Phase (DW)

Mode Select (Mode)

Data bus width

Operating mode select (MMC/SD, SPI, SYSTEST, or MMC SPI protocol).

Power-up control

Clock divider [No clock, 1:255]

SD card only.

This bit (15) must be set following a valid SET_BUS_WIDTH command

(ACMD6) with the value written in bit [1] of the argument. Prior to this

command, the SD card configuration register (SCR) must be verified for the

supported bus width by the SD card.

0: 1-bit data width (DAT[0] used)

1: 4-bit data width (DAT[3:0] used—SD card only).

Value after reset is low.

This bit must always be set to 0 for MMC cards or during SPI transfer. Not set-

ting this bit correctly can result in an unpredictable behavior.

These bits (13-12) select between MMC/SD mode, SPI mode 1, SYSTEST

mode and SPI mode 2.

In MMC/SD mode, transfers to the MMC/SD card follow the MMC protocol.

MMC clock is enabled and the SPI clock is disabled.

In SPI mode1, transfers to up to three SPI controlled devices (serial flash, etc.)

are supported. In this mode, SPI clock is enabled and MMC clock is disabled.

In SYSTEST mode, the signal pins are configured as general-purpose input/

output and the 64-byte FIFO is configured as a stack memory accessible only

by the local host. The pins retain their default type (input, output or in/out).

MMC/SD Host Controller

MPU Public Peripherals