Interrupt Level Registers (Ilr0; Interrupt Control Register (Control_Reg) - Texas Instruments OMAP5910 Technical Reference Manual

Table 8–27. Interrupt Control Register (CONTROL_REG)
Bit Name
1 NEW_FIQ_AGR
0 NEW_IRQ_AGR
Table 8–28. Interrupt Level Registers (ILR0...ILR15)
DSP Word Offset Address (hex)
0x0C
0x0E
:::
0x0C + (N–1)*2
:::
0x2A
Description
New FIQ agreement
Writing a 1 resets FIQ output and clears source FIQ register.
Enables a new FIQ generation, reset by internal logic.
Corresponding bit of ITR must be cleared first.
New IRQ agreement
Writing a 1 resets IRQ output and clears source IRQ register.
Enables a new IRQ generation, reset by internal logic.
Corresponding bit of ITR must be cleared first.
Note: All level 2 DSP interrupts must be configured as FIQ to
generate DSP interrupts because IRQ is not connected.
The software interrupt set register is a 16-bit, read/write register. Writing a 1
to any bit generates an interrupt to the DSP if the corresponding ILR register
is set as edge-triggered; otherwise, no interrupt is generated. A 0 is always
returned from a read to this register. External interrupts are ORed with the
software interrupts before they are sent to the mask interrupt register for
interrupt masking.
Name
ILR_IRQ_0
ILR_IRQ_1
:::
ILR_IRQ_N–1
:::
ILR_IRQ_15
Interrupt Handlers
Type
R/W
R/W
Corresponding Interrupt
IRQ_0
IRQ_1
:::
IRQ_N–1
:::
IRQ_15
DSP Private Peripherals
Reset
Value
0
0
8-23