Translation Table - Texas Instruments OMAP5910 Technical Reference Manual

2.7.2

Translation Table

2.7.3 Domains and Access Permissions
Unpredictable behavior occurs if two TLB entries correspond to overlapping
areas of memory in the virtual space. This can occur if the TLB is not flushed
after the memory is remapped with different-sized pages (leaving an old map-
ping with different sizes in the TLB and using a new mapping that is loaded into
a different TLB location).
The translation table held in main memory has two levels:
-
The first-level table can hold both section translation entries and pointers
to second-level tables (either fine tables or coarse tables).
-
The second-level tables can hold large, small, and tiny page translations
entries.
The MMU also supports domains. Domains are areas of memory that can be
defined to have individual access rights. The CP15 domain access control reg-
ister can specify access rights for up to 16 separate domains. This register is
shared by the instruction access permission logic and data access permission
logic.
When the MMU is disabled, there is no address translation and no memory
access permission checks are performed.
Small pages are further divided into 1K-byte subpages, and large pages are
further divided into 16K-byte subpages with separate access permission
rights.
Tiny pages and sections are not divided into subpages (single access
permission rights).
MPU Memory Management Unit
MPU Subsystem 2-27