Lcd Dedicated Channel - Texas Instruments OMAP5910 Technical Reference Manual

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LCD Dedicated Channel

5.4 LCD Dedicated Channel

Functional Description

Figure 5–10. LCD Channel

IRQ_DMA_CH_LCD

The LCD channel transfers 16-bit data to the LCD controller from a video frame

buffer stored in memory.

The memory source for the LCD dedicated transfer can be either IMIF or

EMIFF. These transfers can be arranged to one or two frames but they are

always done in frame addressing mode. There is no capability for various

addressing modes as in the other channels. The dual-frame mode allows

concurrent transfer and image processing (reload of one frame while another

is being processed).

LCD registers

dma_lcd_ram(15–0)

dma_first_word (17th bit)

dma_lcd_add(5–0)

dma_lcd_un_flow

dma_lcd_ready

dma_lcd_enable

Switching from one frame to another is achieved by loading the top address

of the second frame buffer after the first frame buffer has been fully transferred.

The LCD channel sends the read request on the relevant port according to the

LCD_SOURCE bit.

The LCD_SOURCE bit is read from the DMA_LCD_CTRL register. The dedi-

cated DMA channel contains a 64 by 17-bit words FIFO (asynchronous RAM

built-in). The dma_lcd_first_word that is used as frame synchronizer by the

LCD controller is the 17

Read address

Data (16-bits)

FIFO and LCD

control logic

FIFO bit output. To ensure correct throughput from

Priority (always high)

From/to generic channels