Interrupt Channel Implementation - Texas Instruments OMAP5910 Technical Reference Manual

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Figure 8–5. Interrupt Channel Implementation

When the edge-registration flip-flop is cleared by the asynchronous reset, two

DSP_INTH_CK clock periods must expire before another negative edge tran-

sition can be registered. Thus successive negative transitions must be a mini-

mum of six DSP_INTH_CK clock periods apart in time to be ensured of being

recognized as two separate incidents. This minimal time does not take into

account the processing time of the interrupts once recognized by the DSP

processor, and this time must be taken into account to derive the minimum time

between interrupts from a system perspective.

Asynchronous

Interrupt(N) software-executed

Clear command

Edge-triggered interrupt

Synchronous clear

Interrupt(N) edge-triggered

DSP Interrupt Interface

DSP Private Peripherals