Test Debug Control 0 Register (Test_Dbg_Ctrl_0) - Texas Instruments OMAP5910 Technical Reference Manual

Table 6–47. Voltage Control 0 Register (VOLTAGE_CTRL_0) (Continued)
Bit Name
0 CONF_VOLTAGE_FLASH_R
Table 6–48. Test Debug Control 0 Register (TEST_DBG_CTRL_0)
Bit Name
31–0 RESERVED
Value Description
This bit controls the drive strength
of the OMAP5910 flash interface
I/O. This allows the interface to be
run at 1.8 V nom or 2.75 V nom.
0 Drive strength is 1.80 V
1 Drive strength is 2.75 V
At reset and in compatibility mode,
the interface is set for 2.75-V
operation. This register only
controls the interface in
OMAP5910 mode.
Description
These register is reserved for factory
testing purposes. All bits must be 0 at all
times to avoid errant behavior.
OMAP5910 Configuration Registers
R/W
R/W
R/W
R/W
MPU Private Peripherals
Reset
Value
0x0
Reset
Value
0x00000000
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