Transmit Control Register 2 Configuration - Texas Instruments OMAP5910 Technical Reference Manual

Table 7–89. Transmit Control Register 2 Configuration
Configuration
Bit Value
15 0b
14–8 000 0000b
7–5 000b
4–3 00b
2 0b
1–0 01b
7.10.1.14 Sample Rate Generator Configuration (SRGR[1,2])
7.10.1.15 DMA Configuration
7.10.1.16 Interrupt Flag Configuration and Clear (ILR, MIR)
7.10.1.17 Take out of Reset for Transmit and Receive Starting (SPCR[1,2])
ARM_Write(0x0001) => XCR2; set up XCR2 per below configuration.
Description
Set single-phase frame
Don't care for single-phase frame
Don't care for single-phase frame
Set no companding data and transfer start with MSB first
Set FSX not ignore after the first resets the transfer
Set data delay as 1 bit
1) Configure the sample rate generator appropriately for CLKX and FSX. For
details, see TMS320C54x DSP Enhanced Peripherals Reference Set,
vol. 5, SPRA302.
2) Wait two CLKSRG clocks.
3) ARM_Write SPCR2 or (0x0000 0040)=>SPCR2;CLKG enable.
4) Wait two CLKG clocks.
Configure the REVT and XEVT bit for the DMA receive and transmit
synchronized invent.
1) ARM_Write => ILR; set ILR appropriately for the interrupt handling priority.
2) ARM_Write MIR and (0x0000 0030) => MIR ; disabled SPI TX and RX
interrupt
Note:
Enable the appropriate DMA channel interrupts.
1) ARM_write SPCR1 or (0x0001) => SPCR1; enabled receive port.
2) ARM_write SPCR2 or (0x0001) => SPCR2; enabled transmit port.
MPU Public Peripherals
McBSP2
7-115