Control-And-Status Register (Csr) - Texas Instruments OMAP5910 Reference Manual

Table 4.

Control-and-Status Register (CSR)

Bits Field
15 RDRB
14 CSRB
13 START
12 CS_CMD
11−10 INDEX
SPRU686
Value Description
RDRB bit = 1 indicates that the receive (RDR) area is full.
When the controller reads the content of the RDR, this bit
is cleared.
This bit is read only.
CSRB bit = 0 indicates that the control and status register
(CSR) is ready to receive new data.
After starting a MicroWire transfer with the CSR, this bit is
set to 1. When the corresponding action has been done,
the CSRB is reset. This bit is controlled by a MicroWire
internal state machine running on the F_INT internal clock
(12 MHz/N). If the CSR is read just after being written and
the MPU is running at a high frequency (60 MHz or 120
MHz, for instance) compared to the internal clock, the
CSRB status bit may still be low for the first read access.
The CSRB latency is 0 if the transfer was initiated by
modifying the CS_CMD bit, but it can be 0 −3 cycles if
initiated by the START bit. Some suggested work-arounds
are to: (a) have a few NOPs between initiating a MicroWire
transfer and checking the CSRB status or( b) check that
the CSRB first has a high value on an initial read before it
goes low on a subsequent read.
This bit is read only.
1 Start a write and/or a read process.
This bit is automatically reset by the internal logic when a
write or a read process is activated.
Send the NB_BITS_WR bits (contained in TDR) to the
serial output DO. If the NB_BITS_WR is equal to zero,
then the write process is not started.
Receive the NB_BITS_RD bits from the serial input DI and
store them in the RDR.
1 Set the chip-select of the selected device to its active level.
Index of the external device
00 CS0
01 Reserved
10 Reserved
11 CS3
MicroWire Interface
Reset
Value
Undefined
MicroWire Interface
0
0
0
0
11