Ptv Value And Associated Divisor Value - Texas Instruments OMAP5910 Technical Reference Manual

Table 6–9. PTV Value and Associated Divisor Value
By default, this timer is configured as a watchdog timer and
generates a reset of the TI925T RISC processor approximately
every 19 seconds, unless you disable or update properly. If you do
not, you may during system development encounter an
unexpected reset every 19 seconds or so.
Be certain to disable the watchdog timer before placing the TI925T RISC proc-
essor in deep sleep mode. It must not be left configured as a watchdog timer.
The watchdog timer underflow generates a reset to the TI925T RISC proces-
sor and the C55x DSP processor. If CLKIN is 12 MHz and the watchdog timer
values are left at their power-up state (the value loaded into LOAD_TIM is set
to the maximum value of 0xFFFF at power-up), the reset occurs in approxi-
mately 19 seconds.
The watchdog timer uses a special clock from the MPU clock frequency gener-
ation module (CLKM1). This clock is CLKIN/14. When configured as a watch-
dog timer, the prescaler field (PTV of CNTL_TIMER (reference )) is fixed at 7.
When configured as a general-purpose timer, the prescaler field can range
from 0 to 7. The time from writing a new value to counter underflow is between
256*Tclk to 16,777,216*Tclk, where Tclk = CLKIN/14, for a CLKIN clock
frequency of 12 MHz, and the reset time is: 298 µs < t > 19s.
The timer interrupt period is determined in the following manner, where t
the clock period of the input clock, LOAD_TIM is the register that holds the val-
ue loaded when the timer passes through 0 or when it starts, and PTV is the
prescaler field located in the control timer register (CNTL_TIMER). The value
of the PTV field is forced to 7 if the timer is in watchdog mode.
PTV Divisor
0 2
1 4
2 8
3 16
4 32
5 64
6 128
7 256
MPU Private Peripherals
Watchdog Timer
is
clk
6-9