Write Buffer Configuration; Operation - Texas Instruments OMAP5910 Technical Reference Manual

2.5.1

Operation

The WB operation is controlled by four control bits, as shown in Table 2–2.
Table 2–2. Write Buffer Configuration
C_CP15 W_CP15
0 0
0 1
1 0
1 1
0 1
1 1
1 1
1 1
Note: In copy-back mode with the WB disabled (1011 configuration), dirty lines are saved to the external memory via the WB
regardless of W_CP15. Write misses go directly to the external memory. If the WB is disabled and the system is config-
ured in copy-back mode, only write misses stall the system.
2.5.2 SWAP Instruction
C_MMU B_MMU
X x
X 0
X x
0 0
X 1
0 1
1 0
1 1
When writes are not buffered, the processor stalls until the external write
access is complete.
When bit L of the CP15 TI925T configuration register is set, the write phase
of the SWAP instruction (interlocked read-write) is treated as unbuffered when
data belongs to an noncacheable, nonbuffered (NCNB) or NCB region, even
if it is marked as buffered. The S_LOCK signal is active through the read and
write accesses. If the read of the SWAP instruction hits the cache, S_LOCK
is asserted during the read despite the fact that no external access is
performed. The write is performed both in the cache and externally with
S_LOCK active.
For WT- or CB-mode regions, S_LOCK is not active and accesses are
performed like ordinary read or write accesses.
When bit L of the CP15 TI925T configuration register is reset, S_LOCK stays
low during the SWAP instruction regardless of the memory region type (NCNB,
NCB, WT, or CB). If marked as buffered, data is written to the write buffer and
reaches the system bus after an undetermined delay.
Functional Description
Writes are not buffered.
See Note
Noncacheable, buffered (NCB)
NCB
Writes are buffered, write-through mode.
Writes are buffered, copy-back mode.
MPU Subsystem
Write Buffer
2-9