Asynchronous Read Operation; Fclkdiv Settings And Resulting Emifs Reference Clock - Texas Instruments OMAP5910 Reference Manual

Memory Interfaces
3.2.5

Asynchronous Read Operation

26 Memory Interface Traffic Controller
Table 5. FCLKDIV Settings and Resulting EMIFS Reference
Clock (Continued)
10
11
In the synchronous mode, the active EMIFS clock is output on the FLASH.CLK
pin. In asynchronous mode, the pin is driven inactive low.
In synchronous modes a selectable retiming feature enables read data to be
latched by a delayed EMIFS reference clock. The retiming feature accounts
for delays through the OMAP5910 input/output pins by feeding back
FLASH.CLK to offer optimum data and clock alignment. You can select the
retiming mode using the RT bit in the EMIFS chip-select configuration
registers.
Asynchronous read mode is selected by programming the RDMODE bit field
to 000 in the corresponding EMIF slow chip-select configuration register. This
is the default mode at reset.
The following characteristics describe asynchronous read mode operations:
The chip-select pulse width depends on the RDWST bit field of the EMIFS
-
chip-select configuration register. Pulse width equals:
(RDWST + 2) x EMIFS_Ref (shown as N cycles in Figure 3)
Chip-select minimum pulse width is (2 x EMIFS_Ref).
Address drive time follows FLASH.CS_[X] activation. The FLASH.ADV
-
output is asserted with the address for use with Intel and AMD burst flash
protocols.
Read data is latched on the same TC clock rising edge that deactivates
-
the FLASH.OE signal.
In asynchronous mode, the internal EMIFS reference clock is not provided
-
outside the EMIFS. The FLASH.CLK signal remains low.
Figure 3 shows typical timing for an asynchronous 16-bit read operation
-
on a 16-bit width device with RDWST = 4, FCLKDIV = 01.
TC clock/4
TC clock/6
SPRU673