Asynchronous Page Mode 8X16-Bit Read Operation On A 16-Bit Width Device - Texas Instruments OMAP5910 Reference Manual

Memory Interfaces
Figure 4.

Asynchronous Page Mode 8x16-Bit Read Operation on a 16-Bit Width Device

(8 Words per Page)
TC Clock
(internal)
EMIFS Ref
(internal)
FLASH.CLK
FLASH.CS_[X]
FLASH.ADV
FLASH.A(24:1)
FLASH.D(15:0)
FLASH.OE
FLASH.RDY
FLASH.BE(1:0)
28 Memory Interface Traffic Controller
As in asynchronous mode, device interface signals are referenced to the
internal EMIFS reference clock, which is divided from the TC clock using
FCLKDIV in the EMIF slow interface configuration register. The FLASH.CLK
signal is not externally driven in asynchronous page operating mode.
Figure 4 shows typical timing for an asynchronous page mode 8x16-bit read
operation on a 16-bit width device with RDWST = 2, PGWST = 0,
FCLKDIV = 01, and RDMODE = 2.
Figure 5 shows typical timing for an asynchronous page mode 8x16-bit read
with page crossing on a 16-bit width device with RDWST = 2, PGWST = 0,
FCLKDIV = 01, and RDMODE = 2.
Low
N cycles
P cycles
Add0 Add1
D0 D1
Addr4
Add2 Add3 Add5
D2 D3 D4 D5
High
Add6 Add7
D6 D7
SPRU673