Communication Μ-Law Interface Interrupts Waveform Example - Texas Instruments OMAP5910 Technical Reference Manual

Transmit Data Loading (TX_INT ISR)
Received Data Loading (RX_INT ISR)
Stop MCSI
Figure 9–9. Communication µ-Law Interface Interrupts Waveform Example
CLK
FRM
TXD
T7 T6
RXD
R7 R6 R5 R4
-
DSP_Write(0x0007) = MAIN_PARAMETERS_REG (set up MCSI per
configuration below)
J
Bit 15-14 (00b): No DMA
J
Bit 10 (0b): Positive polarity for frame
J
Bit 9 (0b): Normal synchronization mode
J
Bit 8 (0b): Short framing
J
Bit 7 (0b): Single channel
J
Bit 6 (0b): Slave mode
J
Bit 5 (0b): Burst mode
J
Bit 4 (0b): Positive edge for clock
J
Bit 3-0 (0111b): 8-bit data
-
DSP_Write(0x0700) = INTERRUPTS_REG (all interrupts are enabled)
-
DSP_Write(0x0000) = OVER_CLOCK_REG
-
DSP_Write(0x0001) = CONTROL_REG (start MCSI)
-
DSP_Write = TX_REG
-
DSP_Read = RX_REG
-
DSP_Write(0x0000) = CONTROL_REG (disable MCSI clock)
-
DSP_Write(0x0002) = CONTROL_REG (reset MCSI registers)
T5 T4 T3 T2 T1
R3 R2 R1 R0
T0 T7 T6 T5
R7 R6 R5 R4 R3 R2 R1 R0
DSP Public Peripherals
Multichannel Serial Interfaces
T4 T3 T2 T1 T0
9-31