Memory Representation - Texas Instruments OMAP5910 Technical Reference Manual

Generic Channels
Figure 5–6. Memory Representation
Element n
Frame n
Element n+1
Block n
Frame n+1
5-14
Byte @ addr 00
Byte @ 01
Byte @ 02
Byte @ 03
Byte @ 04
Byte @ 05
Byte @ 06
Byte @ 07
Byte @ 08
Byte @ 09
Byte @ 0A
Byte @ 0B
Byte @ 0C
Byte @ 0D
Byte @ 0E
Byte @ 0F
Byte @ 10
Byte @ 11
Byte @ 12
Byte @ 13
Byte @ 14
Byte @ 15
Byte @ 16
Byte @ 17
MEMORY
The amount of data (block size) to transfer is programmed in bytes. This size
can be odd or even. The start address for a transfer is a byte address and can
be odd—in other words, non-word aligned (this is true only if bursting is not
enabled, because any DMA channel that has bursting enabled must use a start
address that is 32-bit word aligned. Furthermore, a DMA channel using burst-
ing must be configured such that all addresses accessed by that channel are
also 32-bit word aligned). The data block to transfer is split in frames and
elements. The byte size of this data block is:
BS = FN x EN x ES
where:
BS is the block size in bytes.
Element size
(Can be 1, 2, 4. Here: Element size = 4)
Element index (address increments by this
value after an element)
(Can be different from element size)
(Here: Element Index = 3)
Frame index (address increments by this
value after a frame)
(Can be different from element size)
(Here: Frame Index = 5)