Tlb Operations - Texas Instruments OMAP5910 Technical Reference Manual

2.6.2.3

TLB Operations

Table 2–11. TLB Operations
Function
Flush I TLB
Flush I TLB entry
Flush D TLB
Flush D TLB
Flush I + D TLB
2.6.2.4 TLB Lock-Down Registers
The CP15 register 8 is a write-only pseudoregister that manages the transla-
tion look-aside buffers (TLBs). TI925T includes separate instruction and data
TLBs. Several TLB functions are defined and are selected by the opcode_2
and CRm fields.
The flush-I and flush-D functions, respectively, flush (invalidate) all unpres-
erved entries of the instruction and data TLB.
The flush entry functions flush a single entry of the TLB corresponding to the
virtual address present in Rd, regardless of its state (preserved/unpreserved).
All unused values of opcode_2 and CRm are ignored. Reading register 8 is
ignored.
Opcode_2 CRm
0b000 0b0101
0b001 0b0101
0b000 0b0110
0b001 0b0110 VA
0b000 0b0111
There is a TLB lock down register for both TLBs; the value of opcode_2 deter-
mines which TLB register is accessed.
-
Opcode_2 = 0 selects the register associated with the D-TLB.
-
Opcode_2 = 1 selects the register associated with the I-TLB.
Each TLB has its own victim counter. These registers and counters are set to
zero upon reset.
Reading register 10 returns the value of the TLB victim counter base value reg-
ister, the current value of the victim counter, and the state of the preserved bit.
Bits 20–1 are unpredictable when read.
Writing to register 10 updates the base value, the current victim pointer, and
the preserved register value. Bits 20–1 are ignored on write but SBZ.
Rd Instruction
SBZ MCR p15, 0, Rd, c8, c5, 0
VA MCR p15, 0, Rd, c8, c5, 1
SBZ MCR p15, 0, Rd, c8, c6, 0
VA MCR p15, 0, Rd, c8, c6, 1
SBZ MCR p15, 0, Rd, c8, c7, 0
MPU Subsystem
Coprocessor 15
2-21