Time-Out 1 Register (Timeout1); Time-Out 2 Register (Timeout2); Time-Out 3 Register (Timeout3) - Texas Instruments OMAP5910 Technical Reference Manual

Traffic Controller Memory Interface Registers
Table 4–22. Time-Out 1 Register (TIMEOUT1)
Bit Field
31–24 Reserved
23–16 Local bus
15:8 Reserved
7:0 DMA
Table 4–23. Time-Out 2 Register (TIMEOUT2)
Bit Field
31–24 Reserved
23–16 DSP
15–8 Reserved
7–0 LCD
Table 4–24. Time-Out 3 Register (TIMEOUT3)
Bit Field
31–0 Reserved
4-54
The three time-out registers store the number of clock cycles before DSP,
DMA, LCD, LB requests are made high-priority in dynamic priority scheme for
the TC (see Table 4–22 through Table 4–24).
Description
Read is undefined. Writes must be zero.
Read is undefined. Writes must be zero.
Description
Read is undefined. Writes must be zero.
Read is undefined. Writes must be zero.
Description
Read is undefined. Writes must be zero.
Reset
Access
Value
R All 0
R/W 0x00
R/W All 0
R/W 0x00
Reset
Access
Value
R All 0
R/W 0x00
R/W All 0
R/W 0x00
Reset
Access
Value
R All 0