Camera Interface - Texas Instruments OMAP5910 Technical Reference Manual

7.2 Camera Interface

7.2.1 Functional Architecture
An 8-bit camera interface (32-bit internal bus on the TIPB side) connects a
camera module to the MPU peripheral bus of the OMAP5910 device. The in-
terface handles multiple image formats synchronized on vertical and horizon-
tal synchronization signals. Data transfer between camera and interface can
be done synchronously or asynchronously. The data is stored in a buffer to be
sent over the peripheral bus using DMA mode or CPU mode (bypass mode).
The interface supports 8-bit parallel image data ports and horizontal/vertical
signal ports separately (stand-alone synchronous method). The camera
interface has a DMA port.
The architecture consists of four functional blocks:
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Buffer:
A buffer is used to store the data word received from the camera module
and transfer it to the MPU peripheral bridge using the DMA mode or the
CPU mode. It contains a 128-word FIFO.
The 8-bit data received from the camera module is latched and mixed to be
compliant with the 32-bit data format of the MPU TIPB. A 128-bit-deep
FIFO is implemented to provide local buffering of data and to control the
DMA request when the camera interface is enabled in DMA mode. The
main goals of this mode are:
J
To discharge CPU of the data transfer
J
To reduce real time constraints of DMA read (FIFO's buffering part)
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To group x DMA accesses in only one time slot (FIFO's block part)
It is, however, possible to forward a direct transfer to the CPU in bypass
mode by disabling the DMA request line.
-
Clock divider:
This function is mainly used to manage clock division and to handle
external clock generation for synchronous/asynchronous mode gating.
-
Interrupt generator:
An interrupt is generated to indicate start and end of frame, start and end of
image, and FIFO overflow.
-
TIPB registers:
Status, control, and data 32-bit registers connect via the TIPB.
Camera Interface
MPU Public Peripherals 7-3