I-Cache Ram Set Control Registers (Rcr1 And Rcr2) - Texas Instruments OMAP5910 Reference Manual

Instruction Cache
Figure 15.

I-Cache RAM Set Control Registers (RCR1 and RCR2)

RCR1
15 14
TAG_
VALID
R-0
RCR2
15 14
TAG_
VALID
R-0
Note: R = Read, W = Write; −n = Value after reset;, −x = Value after reset is not defined
54 DSP Subsystem
Tag-valid bit (TAG_VALID). When the I-Cache completes the process of
-
filling a RAM set, the I-Cache sets TAG_VALID in that RAM set's control
register. You can poll this bit to determine when the RAM set is ready.
Note:
On OMAP5910 and OMAP5912, you must always set FLUSH and ENABLE
in RCR1 and RCR2.
Reserved
R-0x3
Reserved
R-0x3
2 1
FLUSH ENABLE
RW-0
2 1
FLUSH ENABLE
RW-0
SPRU890A
0
RW-1
0
RW-1