Tc Block Diagram - Texas Instruments OMAP5910 Reference Manual

Dual-core processor memory interface traffic controller
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Introduction
Figure 1.

TC Block Diagram

OMAP5910
DSP
MMU
ROM
E
FLASH
16
M
and
I
SRAM
F
memories
S
E
Memory
16
M
interface
SDRAM
I
memories
F
controller
F
I
M
I
F
32
SRAM
MPU core
1.5 M
bits
(instruction
cache, data
cache, MMU)
JTAG
emulation
I/F
12
Memory Interface Traffic Controller
TMS320C55x DSP
32
(instruction cache,
SARAM, DARAM, DMA,
H/W accelerators)
16
MPU
interface
32
32
MPU bus
32
32
System
32
DMA
traffic
32
controller
(TC)
16
32
32
(TI925T)
LCD
ETM9
I/F
Osc
12 MHz
or 13 MHz
DSP private
DSP private
peripherals
peripheral
Timers (3)
bus
Watchdog timer
16
Level1/2
interrupt handlers
DSP public (shared) peripheral bus
16
32
MPU
peripheral
bridge
32
32
MPU private peripheral bus
MPU private
peripherals
Timers (3)
Watchdog timer
Level 1/2 interrupt
Clock and reset
management
Configuration
Osc
identification
External
Clock
clock
32
request
KHz
Reset
DSP public peripherals
McBSP1
McBSP3
MCSI1
MCSI2
MPU/DSP shared peripherals
Mailbox
GPIO I/F
UART1
TIPB
UART2
switch
UART3 IrDA
MPU public
peripheral
MPU public peripherals
bus
McBSP2
USB host I/F
MSB function I/F
2
I
C
µWire
Camera I/F
MPUIO
32 KHz timer
PWT
PWL
Keyboard I/F
MMC/SD
LPG x2
Frame adjustment
handlers
counter
HDQ/1-WIRE
registers
RTC
Device
SPRU673

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