Overview - Texas Instruments OMAP5910 Reference Manual

7 DSP DMA
7.1

Overview

7.1.1 Purpose of the DSP DMA
7.1.2 Features
SPRU890A
Acting in the background of DSP core operation, the DMA controller can:
Transfer data among internal memory, DSP external memory, and
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peripherals residing on the DSP public peripheral bus
Transfer data between the Microprocessor Unit Interface (MPUI) and
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memory internal to the DSP subsystem
The DMA controller has the following important features:
Operation that is independent of the DSP core
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Four standard ports, one for each data resource: internal dual-access
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RAM (DARAM), internal single-access RAM (SARAM), DSP external
memory (via the External Memory Interface [EMIF]), and peripherals (via
the shared TI peripheral bus bridge)
An auxiliary port to enable certain transfers between the MPUI and
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memory
Six channels, which allow the DMA controller to keep track of the context
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of six independent block transfers among the standard ports
Bits for assigning each channel a low priority or a high priority. For details,
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see section 7.2.6, Service Chain.
Event synchronization. DMA transfers in each channel can be made
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dependent on the occurrence of selected events. For details, see section
7.2.12, Synchronizing Channel Activity.
An interrupt for each channel. Each channel can send an interrupt to the
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DSP core on completion of certain operational events. See section 7.2.15,
Interrupt Support.
Software-selectable options for updating addresses for the sources and
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destinations of data transfers.
A dedicated idle domain. The DMA controller can be put into a low-power
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state by turning off this domain. Each multichannel buffered serial port
(McBSP) has the ability to temporarily take the DMA domain out of this idle
state when the McBSP needs the DMA controller. See Power
Management in section 7.2.16.
To read about the registers that program the DMA controller, see section 7.3.
DSP DMA
DSP Subsystem 121