Dsp Level 2 Interrupt Mapping - Texas Instruments OMAP5910 Technical Reference Manual

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8.4.2.3
Level 2 Interrupt Mapping
Table 8–30. DSP Level 2 Interrupt Mapping
Incoming Interrupts
McBSP3 TX
McBSP3 RX
McBSP1 TX
McBSP1 RX
UART2
UART1
MCSI1 TX
MCSI1 RX
MSCI2 TX
MCSI2 RX
MCSI1 frame error
MCSI2 frame error
Reserved
Reserved
Reserved
Reserved
Table 8–30 shows the DSP level 2 interrupt mapping.
Required Sensitivity Setup
Level-sensitive interrupts are level-active; the interrupt line must remain
asserted until it has been acknowledged.
Edge-triggered interrupts are edge-triggered; just an edge is required for gen-
erating the interrupt. The interrupt to the DSP is cleared upon reading of the
interrupt registers or writing a 0 to the interrupt mask registers in the interrupt
handler.
Edge
Edge
Edge
Edge
Level
Level
Level
Level
Level
Level
Level
Level
DSP Private Peripherals
Interrupt Handlers
Level 2 Interrupt
IRQ_00
IRQ_01
IRQ_02
IRQ_03
IRQ_04
IRQ_05
IRQ_06
IRQ_07
IRQ_08
IRQ_09
IRQ_10
IRQ_11
IRQ_12
IRQ_13
IRQ_14
IRQ_15
8-25

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