Page 1 OMAP5910 Dual-Core Processor Technical Reference Manual Literature Number: SPRU602B January 2003...
Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
Page 3: Read This First
About This Manual This manual describes the Texas Instruments OMAP5910 multimedia proces- sor, hereafter called the OMAP5910 device. The OMAP5910 device supports the development and testing of wireless device applications that use the Microsoft Windows CE or the Symbian EPOC operating system.This manual...
Page 4 Notational Conventions In syntax descriptions, the instruction, command, or directive is in a bold typeface font and parameters are in an italic typeface. Portions of a syntax that are in bold should be entered as shown; portions of a syntax that are in italics describe the type of information that should be entered.
Page 5 Information About Cautions and Warnings / Related Documentation From Texas Instruments Notational Conventions Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
Page 6 Bluetooth is a trademark owned by the Bluetooth SIG, Inc. and licensed to Texas Instruments. TMS320C5510, TMS320C55x, C55x, and Code Composer Studio are trademarks of Texas Instruments. Microsoft, Windows, Windows CE, Windows CE Platform Builder, and Windows NT are trademarks of Microsoft Corporation.
Page 7: Table Of Contents
..............Introduces the setup, components, and features of the OMAP5910 processor and provides a high-level view of the device architecture.
Page 8 ..............Describes the OMAP5910 multimedia processor DSP subsystem.
Page 9 ..........Describes the OMAP5910 multimedia processor memory interface traffic controller (TC).
Page 10 ............Describes the OMAP5910 multimedia processor MPU private peripherals.
Page 11 ..........7-57 7.8.2 OMAP5910 I2C (Master/Slave I2C Controller) ......7-64 7.8.3...
Page 12 ............Describes the DSP private peripherals for the OMAP5910 multimedia processor.
Page 13 ........... . 10-1 Describes the MPU/DSP shared peripherals for the OMAP5910 multimedia processor. 10.1 Introduction .
Page 14 ..............12-1 Describes the universal asynchronous receiver/transmitter (UART) devices in the OMAP5910 multimedia processor.
Page 15 ............13-1 Describes the components and features of the OMAP5910 universal serial bus (USB) function module.
Page 16 ............14-1 Describes the universal serial bus (USB) host of the OMAP5910 multimedia processor. 14.1 USB Host Controller .
Page 17 ... 14-49 14.5.3 On-Board Transceiverless Connection Using OMAP5910 Transceiverless Link Logic ......... .
Page 18 ............Describes the programming guidelines for switching clock modes in the OMAP5910 device.
Page 19 Figures OMAP5910 Master Block Diagram ..........
Page 20 Figures TC Block Diagram ............. Traffic Controller .
Page 21 Figures FIFO Buffer Parts ............. IRQ Generated on VSYNC Falling Edge .
Page 22 Figures 7-54 Initialization Phase ............7-162 7-55 Detail of Basic Operation...
Page 23 11-1 LCD Controller on Board the OMAP5910 Device ....... . .
Page 24 Figures 12-18 Receive FIFO IT Request Generation ......... . 12-91 12-19 Transmit FIFO IT Request Generation .
Page 25 ..... . . 14-79 14-32 OMAP5910 USB Host Controller Data Path to System Memory ....
Page 26 Figures 15-1 OMAP5910 Device Clock and Reset Management ....... 15-2...
Page 27 Tables Tables Data Cache Configuration ............Write Buffer Configuration .
Page 28 Tables 2-42 Global Flush Register (GFLUSH_REG) - Offset Address (hex): 3C ....2-53 2-43 Individual Flush Register (FLUSH_ENTRY_REG) - Offset Address (hex):40 ..2-53 2-44 CAM Entry Register MSB (READ_CAM_H_REG) - Offset Address (hex): 44...
Page 29 Tables Controller Access Mode and Data Access Width ........Device Types Associated With Chip-Select .
Page 30 ......... . 6-13 6-16 Level 1 and Level 2 OMAP5910 MPU Interrupt Mapping ......6-17...
Page 31 Tables 6-26 Configuration Registers ............6-27 6-27 Functional Multiplexing Control 0 Register (FUNC_MUX_CTRL_0)
Page 32 Tables 7-22 Keyboard Mask Interrupt Register (KBD_ MASKIT) ....... 7-28 7-23 GPIO Mask Interrupt Register (GPIO_MASKIT) .
Page 33 Tables 7-70 I2C SCL High Time Control Register (I2C_SCLH) ....... . 7-84 7-71 I2C System Test Register (I2C_SYSTEST)
Page 34 Tables 7-1 18 MMC/SD Command Response Register 3 (MMC_RSP3) ......7-159 7-1 19 MMC/SD Command Response Register 4 (MMC_RSP4) .
Page 35 Tables 8-16 DSP Watchdog Timer Registers ..........8-13 8-17 Control Timer Register (CNTL_TIMER)
Page 36 Tables 9-28 Transmit Control Register 2 Configuration (DSP_Write(0x0000) => XCR2) ..9-25 9-29 Channel Selection Register (CHANNEL_USED_REG) ......9-44 9-30 Clock Frequency Register (CLOCK_FREQUENCY_REG)
Page 37 Tables 11-21 Minimum Pixel Clock Divider (PCD) ......... . . 11-45 11-22 LCD Status Register (LcdStatus)
Page 38 Tables 12-45 Receive Holding Register (RHR) ..........12-55 12-46 Transmit Holding Register (THR) .
Page 39 Tables 13-1 USB Function Module Registers ..........13-9 13-2 Revision Register (REV)
Page 40 Tables 14-23 HC Port 1 Status and Control Register (HcRhPortStatus1) ......14-30 14-24 HC Port 2 Status and Control Register (HcRhPortStatus2) .
Page 41 15-83 Input and Output Signals for the OMAP5910 Device .......
Page 42: Introduction
Chapter 1 Introduction This chapter introduces the setup, components, and features of the OMAP5910 processor and provides a high-level view of the device architecture. Topic Page Overview ........... . .
Page 43 TI TMS320C55x DSP, peripherals, and other components. The OMAP5910 processor is available in the small 289-pin MicroStar package (12 x 12 mm). Figure 1–1 is a master block diagram of the 289-pin OMAP5910 processor. Figure 1–2 shows the OMAP5910 in more detail.
Page 44: Omap5910 Master Block Diagram
Overview Figure 1–1. OMAP5910 Master Block Diagram DSP private Private peripherals OMAP5910 peripheral bus Timers (3) DSP public peripherals Watchdog timer TMS320C55x DSP Level 1/2 McBSP1 interrupt handlers (Instruction cache, SARAM DARAM, DMA, McBSP3 H/W accelerators) DSP public (shared) pheripheral bus...
Page 45: Description
TMS320C55x DSP core and a high-performance TI925T core. The OMAP5910 device is designed to run leading open and embedded RISC- based operating systems, as well as the Texas Instruments (TI) DSP/BIOS software kernel foundation, and is available in a 289-ball MicroStar BGA package.
Page 46: Omap5910 Diagram
As a system real-time time clock, there are two possible solutions: The OMAP5910 internal solution (internal RTC and 32-kHz oscillator pads) is not a low-power solution, because the OMAP5910 RTC power supply is not separate from the OMAP5910 core power supply.
Page 47: Features
Features 1.3 Features The OMAP5910 device has the following features: Ability to support reduced instruction set computer (RISC) and DSP operating systems TI925T MPU subsystem with: Instruction cache (16K bytes) and data cache (8K bytes) Memory management unit (MMU) A 17-word write buffer (WB) DSP subsystem (C55x...
Page 48 Features 192K bytes of 32-bit-wide internal SRAM memory that allows local storage of operating system (OS) critical routines and that provides a direct path from the SRAM to the LCD controller An external memory traffic controller (TC) that allows asynchronous operation among the external memory interface, the MPU, and the DSP Mailboxes (two for MPU-to-DSP and two for DSP-to-MPU) for interprocessor communication...
Page 49: Architecture
Fourteen general-purpose input/output (GPIO) Mailbox 1.4 Architecture The OMAP5910 device includes the MPU subsystem, the DSP subsystem, a memory interface traffic controller, general-purpose peripherals, dedicated multimedia application (MMA) peripherals, and multiple interfaces. The MPU is the master of the platform, and it has access to the entire 16M bytes of memory space and to the 128K bytes of I/O space of the DSP subsystem.
Page 50: Memory Maps
Memory Maps 1.5 Memory Maps Figure 1–3 shows the MPU memory map. Figure 1–4 shows the DSP memory map. Figure 1–3. MPU Memory Map 0x0000 0000 External slow memory interface Flash space (cs0, cs1, cs2, cs3) 0x1000 0000 SDRAM space External fast memory interface 0x2000 0000 Internal SRAM...
Page 51: Dsp Memory Map
Memory Maps Figure 1–4. DSP Memory Map Byte Address Size 000000h Dual-access DARAM 64K bytes random access memory 010000h Single-access SARAM 96K bytes random access memory 028000h External memory 4M bytes less External CE0 space 160K bytes 400000h External Memory 4M bytes External CE1 space...
Page 52: Software Compatibility
Software Compatibility 1.6 Software Compatibility Code compatibility with future OMAP59x devices is only possible if driver writers adhere to the conventions detailed in Section 1.6.1. 1.6.1 OMAP Driver Compatibility Conventions All locations marked as reserved or unused in the documentation are written as zero, and, in general, values read from reserved locations are not used.
Page 53: Mpu Subsystem
Chapter 2 MPU Subsystem This chapter describes the core, caches, memory management units (MMUs), interface, and bridges of the OMAP5910 multimedia processor microprocessor unit (MPU) subsystem. Topic Page Introduction ..........
Page 54: Clock Generation And System Reset Management
Introduction 2.1 Introduction The MPU of the OMAP5910 device controls the memory management units (MMUs), the system direct memory access (DMA) controller, the MPU TI peripheral bus (TIPB) bridge, and peripherals. Figure 2–1 shows the OMAP5910 device with the MPU subsystem high- lighted.
Page 55: Highlight Of Mpu Subsystem
Introduction Figure 2–1. Highlight of MPU Subsystem DSP private Private peripherals OMAP5910 peripheral bus Timers (3) DSP public peripherals Watchdog timer TMS320C55x DSP Level 1/2 McBSP1 interrupt handlers (Instruction cache, SARAM DARAM, DMA, McBSP3 H/W accelerators) DSP public (shared) pheripheral bus...
Page 56: Mpu Core
A 17-word write buffer (WB) A local bus interface The OMAP5910 device uses the TI925T core in little endian mode only. To reduce effective memory access time, the TI925T has an instruction cache, a data cache, and a write buffer. In general, these are transparent to program...
Page 57: Instruction Cache
Instruction Cache 2.3 Instruction Cache The 16K-byte instruction cache (I-cache) has 1024 lines of 16 bytes arranged as a two-way set-associative cache. It uses the virtual addresses generated by the processor core. The I-cache is always reloaded one line at a time. It can be enabled or disabled via the CP15 control register (I_CP15 bit) and is disabled and flushed upon reset.
Page 58: Data Cache Configuration
Data Cache 2.4 Data Cache The 8K-byte data cache (D-cache) has 512 lines of 16 bytes arranged as a two-way set-associative cache. It uses the virtual addresses generated by the processor. The D-cache is always reloaded one line at a time, because it always requires the MMU to be enabled.
Page 59: Validity
Data Cache Table 2–1. Data Cache Configuration (Continued) C_CP15 C_MMU B_MMU Functional Description Cache search active: write through mode (WT) • Read hits do not generate external accesses. • Write hits update the cache and the external memory. • Read misses cause a line load. •...
Page 60: Double-Mapped Space
Write Buffer Data Cache / Write Buffer Note: Cleaning is not the same as flushing. The entire D-cache can be invalidated with a single flush D-cache instruction through the CP15 cache operation register. The D-cache is flushed upon reset. If the D-cache is disabled, its content is maintained valid and is accessible when the cache is reenabled.
Page 61: Write Buffer Configuration
Write Buffer 2.5.1 Operation The WB operation is controlled by four control bits, as shown in Table 2–2. Table 2–2. Write Buffer Configuration C_CP15 W_CP15 C_MMU B_MMU Functional Description Writes are not buffered. See Note Noncacheable, buffered (NCB) Writes are buffered, write-through mode. Writes are buffered, copy-back mode.
Page 62: Mrc, Mcr Bit Pattern
Coprocessor 15 2.6 Coprocessor 15 TI925T operation and configuration are controlled with coprocessor instruc- tions, configuration pins, and the MMU translation tables. The coprocessor in- structions manipulate on-chip registers, which control the configuration of the cache memories, write buffer, MMU, and a number of other options described in the following sections.
Page 63: Cp15 Register Summary
Coprocessor 15 Ignored: Writing to such a location does not affect the system behavior. VA: Virtual address (data or instruction) In all cases, reading data values from or writing any data values to any CP15 register, including those fields specified as unpredictable or SBZ, causes no permanent damage to the TI925T.
Page 64: Cp15 Id Register
Coprocessor 15 Table 2–4. Reading From CP15 Register 0 Function Opcode_2 Instruction † Read ID 0bXXX 0bXXXX TI925T ID MRC p15, 0, Rd, c0, c0, 0 Read CIR 0b001 0b0000 Cache info MRC p15, 0, Rd, c0, c0, 1 † All opcodes [opcode_2,CRm] except [1,0] return the TI925T ID. Table 2–5.
Page 65 Coprocessor 15 Table 2–6. CP15 Cache Information Register (CIR) (Continued) Name Value Function D-Cache information Parameter to calculate the real D-cache associativity and size: D-cache associativity and D-cache size = base value D-cache associativity and D-cache size = 3/2 of the base value. Exception: If base value of associativity is 1, a 1 indicates that there is no D-cache and 0 indicates that D-cache is really direct-map.
Page 66: Cp15 Control Register
Coprocessor 15 Table 2–6. CP15 Cache Information Register (CIR) (Continued) Name Value Function I-cache information Parameter to calculate the real I-cache associativity and size: I-cache associativity and I-cache size are equal to the base value. I-cache associativity and I-cache size are equal to 3/2 of the base value.
Page 67 System protection. This bit modifies the MMU protection system (see Table 2–24). Little/big endian configuration. The TI925T on the OMAP5910 device supports only little endian mode due to the system architecture of the device. This bit must always be written as 0.
Page 68 Coprocessor 15 Table 2–7. CP15 Control Register (Continued) Name Value Function Memory management unit (MMU) enable/disable MMU disabled MMU enabled The MMU must be enabled before or at the same time as the data cache (C) and write buffer (W). The instruction cache can be enabled independently.
Page 69: Format Of The Cp15 Translation Table Base Register
Coprocessor 15 Figure 2–3. Format of the CP15 Translation Table Base Register Translation Table Base UNP/SBZ Reading from CP15 register 2 returns the pointer to the currently active first- level translation table in bits 31 – 14 and an unpredictable value in bits 13 – 0. The CRm and opcode_2 fields are SBZ when reading this register.
Page 70: Domain Configuration
Coprocessor 15 Table 2–8. Domain Configuration Value Access Type Description 0b00 No access Any access generates a domain fault. 0b01 Client Access rights are checked against the permission given by the page descriptor. 0b10 Reserved Behaves like no access 0b11 Manager The access rights are not checked;...
Page 71: Format Of The Fault Address Register
Coprocessor 15 Figure 2–5. Format of the Fault Address Register Fault Address Reading CP15 register 6 returns the value of the fault address register (FAR). The FAR holds the virtual address of the access that was attempted when a fault occurred. The FAR is only updated for data access faults, not for instruc- tion fetch faults.
Page 72: D-Cache Clean/Flush Single Entry Operand Format
Coprocessor 15 Table 2–10. Cache Operations (Continued) Function Opcode_2 Instruction Clean D-cache entry 0b010 0b1010 Set/Index MCR p15, 0, Rd, c7, c10, 2 Clean and flush D-cache entry 0b010 0b1110 Set/Index MCR p15, 0, Rd, c7, c14, 2 Clean D-cache 0b000 0b1010 MCR p15, 0, Rd, c7, c10, 0...
Page 73: Tlb Operations
Coprocessor 15 2.6.2.3 TLB Operations The CP15 register 8 is a write-only pseudoregister that manages the transla- tion look-aside buffers (TLBs). TI925T includes separate instruction and data TLBs. Several TLB functions are defined and are selected by the opcode_2 and CRm fields. The flush-I and flush-D functions, respectively, flush (invalidate) all unpres- erved entries of the instruction and data TLB.
Page 74: Format Of The Lock-Down Registers
Coprocessor 15 Table 2–12. Lockdown Operations Function Opcode_2 Data Instruction Read D-TLB lock 0b000 0b0000 Value MRC p15, 0, Rd, c10, c0, 0 Write D-TLB lock 0b000 0b0000 Value MCR p15, 0, Rd, c10, c0, 0 Read I-TLB lock 0b001 0b0000 Value MRC p15, 0, Rd, c10, c0, 1...
Page 75: Ti Operations
Coprocessor 15 2.6.2.5 Context Switch (or PID: Process Identifier) Register The PID register is used in Windows CE mode only. The register is used in con- junction with the fast-context switch hardware support and is only used when the Windows CE mode bit is enabled. More information is available upon request.
Page 76 Coprocessor 15 Table 2–14. TI925T Configuration Register (Continued) Name Value Function Must be written to as 0. OS configuration. This bit takes the value of the OS_TYPE input signal upon reset. It is dependent on the hardware application and may be changed by software.
Page 77: Format Of The I_Min And I_Max Registers
Coprocessor 15 Figure 2–8. Format of the I_min and I_max Registers UNP/SBZ l_min UNP/SBZ UNP/SBZ l_max UNP/SBZ I_max indicates the maximum index of the data cache containing a dirty line. I_min indicates the minimum index of the data cache containing a dirty line. Upon reset, D-cache flush or end of the full D-cache clean, the value of I_max is cleared and the value of all the I_min bits is set to 1.
Page 78: Mpu Memory Management Unit
MPU Memory Management Unit 2.7 MPU Memory Management Unit The MPU MMU performs virtual-to-physical address translations and access permission checks for access to the system memory, and it provides the flexi- bility and security required for the OS to manage physical memory space shared by the DSP subsystem and the MPU subsystem.
Page 79: Translation Table
MPU Memory Management Unit Unpredictable behavior occurs if two TLB entries correspond to overlapping areas of memory in the virtual space. This can occur if the TLB is not flushed after the memory is remapped with different-sized pages (leaving an old map- ping with different sizes in the TLB and using a new mapping that is loaded into a different TLB location).
Page 80: Cp15 Registers Or Functions Used By The Mmu
MPU Memory Management Unit 2.7.4 MMU Program-Accessible Registers The system control coprocessor (CP15) registers listed in Table 2–16, in con- junction with the translation tables stored in memory, determine the operation of the MMU or hold the MMU state for access by the processor. Table 2–16.
Page 81: Address Translation Process
MPU Memory Management Unit 2.7.6 Translation Process The MMU translates virtual addresses generated by the CPU into physical addresses to access the external memory and checks the access permission using a translation look-aside buffer (TLB) (see Figure 2–10). The MMU table walking hardware is used to add entries to the TLB. Figure 2–10.
Page 82: Translation Table Base Register
MPU Memory Management Unit 2.7.6.1 Translation Table Base The translation process is initiated when the on-chip TLB does not contain an entry corresponding to the requested virtual address (that is, when a TLB-miss occurs). The CP15 translation table base (TTB) register points to the base of a table in physical memory, which contains section and page table descriptors.
Page 83: Accessing The Translation Table Level 1 Descriptors
MPU Memory Management Unit 2.7.6.2 Level 1 Fetch Bits 31–14 of the TTB register are concatenated with bits 31–20 of the virtual address to produce a 30-bit address (see Figure 2–12) by accessing the translation table level 1 descriptors (see Section 2.7.6.3). This address selects a four-byte translation table entry, which is a level 1 descriptor for either a section or a page table.
Page 84: Level 1 Descriptors
MPU Memory Management Unit 2.7.6.3 Level 1 Descriptor The level 1 descriptor returned is either a coarse or fine page table descriptor or a section descriptor. Its format varies accordingly, as shown in Figure 2–13. Figure 2–13. Level 1 Descriptors 2019 12 11 10 9 8 5 4 3 2 1...
Page 85: Level 1 Coarse Page Table Descriptor
MPU Memory Management Unit Table 2–19. Level 1 Coarse Page Table Descriptor Name Function 31–10 COARSE_PG_BASE Base address used to access the coarse page table entry. The coarse page table index selecting an entry is derived from the virtual address. If a page table descriptor is returned from the level 1 fetch (Bit 0 = 1), a level 2 fetch is initiated.
Page 86: Section Translation
MPU Memory Management Unit 2.7.6.4 Translating Section References Figure 2–14 illustrates the complete section translation sequence. The access permissions contained in the level 1 descriptor must be checked before the physical address is put on the address bus. Figure 2–14. Section Translation Virtual address 20 19 Table index...
Page 87: Page Table Entry (Level 2 Descriptor)
MPU Memory Management Unit 2.7.6.5 Level 2 Descriptor The level 1 fetch, when returning a coarse or fine page table descriptor, pro- vides the base address of the page table to be used. The page table is then accessed, and a level 2 descriptor is returned. This descriptor defines a tiny, small, or large page access.
Page 88: Interpreting Page Table Entry Bits
MPU Memory Management Unit Table 2–22. Interpreting Page Table Entry Bits 1–0 Value Meaning Notes Invalid Generates a page translation fault Large page Indicates a 64K-byte page Small page Indicates a 4K-byte page Tiny page Indicates a 1K-byte page 2.7.6.6 Translating Tiny Pages References Figure 2–16 illustrates the complete translation sequence for a 1K-byte tiny page.
Page 89: Tiny Page Translation
MPU Memory Management Unit Figure 2–16. Tiny Page Translation Virtual address 20 19 10 9 Table index L2 table index Page index Translation table index 14 13 Translation base 14 13 Translation base Table index First-level descriptor Fine page table base address Domain 12 11 Page table base address...
Page 90: Small Page Translation
MPU Memory Management Unit 2.7.6.7 Translating Small Page References Figure 2–17 illustrates the complete translation sequence for a 4K-byte small page. If a small page descriptor is included in a fine page table, the upper two bits of the index of the page overlap the lower two bits of the index of the fine page table.
Page 91: Mmu Faults And Mpu Aborts
MPU Memory Management Unit 2.7.6.8 Translating Large Page References Figure 2–18 illustrates the complete translation sequence for a 64K-byte large page. As the upper four bits of the page index and the lower four bits of the coarse page table index overlap, each coarse page table entry for a large page descriptor must be duplicated 16 times (in consecutive memory locations).
Page 92: Large Page Translation
MPU Memory Management Unit Figure 2–18. Large Page Translation Virtual address 20 19 16 15 12 11 Table index Page index L2 table index Translation table base 14 13 Translation base 14 13 Translation base Table index First-level descriptor Page table base address Domain 10 9 Page table base address...
Page 93: Priority Encoding Of The Fault Status Register
MPU Memory Management Unit 2.7.8 Fault Address and Fault Status Registers (FAR and FSR) If an illegal data access (data abort) occurs, the MMU places an encoded 4-bit value FS[3–0] and the 4-bit encoded domain number in the fault status register (FSR).
Page 94: Domain Access Control Register Format
MPU Memory Management Unit 2.7.9 Domain Access Control MMU accesses are primarily controlled via domains. There are 16 domains, and each domain has a 2-bit field to define it. Two kinds of users are supported: clients and managers. Clients use a domain; managers control the behavior of the domain.
Page 95: Interpreting Access Permission
MPU Memory Management Unit 2.7.10 Permission Access Both instructions and data need access permission checks, but their respec- tive access violations are handled differently. A data access error generates a DABORT and stores the status, domain, and address in FSR and FAR. An instruction fetch generates an IABORT only;...
Page 96: Sequence For Checking Faults
MPU Memory Management Unit Figure 2–20. Sequence for Checking Faults Virtual address Alignment Check address alignment Misaligned fault Section Get level 1 descriptor transistor Invalid fault Section Page Page Get page Invalid translation table entry fault Page Section No access (D0) No access (D0) domain Check domain status...
Page 97: Nonaligned Read Word Access
MPU Memory Management Unit If the access generates an alignment fault, the access sequence aborts with- out checking access rights. If a nonaligned read access is executed and the alignment fault is disabled, data is accessed at a word address and rotated inside the core as shown be- low.
Page 98: External Aborts
MPU Memory Management Unit Section: If the level 1 descriptor defines a section-mapped access, its AP bits define whether or not the the access is allowed (see Table 2–24). Their interpretation is dependent upon the setting of the S bit (CP15 con- trol register bit 8).
Page 99: Dsp Memory Management Unit Registers
The 16M bytes of DSP external addresses can be mapped to any of the 4G bytes of addresses on the OMAP5910 device. If a memory protection or memory access violation occurs, the DSP MMU sends an interrupt to the MPU via the second-level interrupt handler on IRQ_28.
Page 100: Prefetch Register (Prefetch_Reg)) - Offset Address (Hex)
DSP Memory Management Unit Table 2–26. DSP Memory Management Unit Registers (Continued) Name Description Size Address Reset Value RAM_L_REG RAM entry register LSB 16 bits FFFE:D238 0x0000 GFLUSH_REG Global flush register 16 bits FFFE:D23C 0x0000 FLUSH_ENTRY_REG Individual flush register 16 bits FFFE:D240 0x0000 READ_CAM_H_REG Read CAM MSB...
Page 101: Control Register (Cntl_Reg) - Offset Address (Hex)
DSP Memory Management Unit Table 2–29. Control Register (CNTL_REG) – Offset Address (hex): 08 Value at Hardware Reset Function Size Access 15–6 Reserved Enables the 16-bit burst management. Active high. Reserved Reserved When 1, enables the walking table logic. When 0, the walking table is disabled and access to the TLB and lock counter are disabled.
Page 102: Fault Status Register (F_St_Reg)) - Offset Address (Hex)
DSP Memory Management Unit Table 2–32. Fault Status Register (F_ST_REG)) – Offset Address (hex): 14 Value at Hardware Reset Function Size Access 15–4 Reserved Error occurred during a prefetch. Active high. Permission fault. Active high. TLB miss. Active high. Translation fault. Active high. Table 2–33.
Page 103: Lock Counter Register (Lock_Reg) - Offset Address (Hex)
DSP Memory Management Unit Table 2–36. Lock Counter Register (LOCK_REG) – Offset Address (hex): 24 Value at Hardware Function Size Access Reset 15–10 Locked entries base value 9–4 Current entry pointed by the WTL 3–0 Reserved Table 2–37. Load Entry in TLB Register (LD_TLB_REG) – Offset Address (hex): 28 Value at Hardware Function...
Page 104: Cam Entry Register Lsb (Cam_L_Reg) - Offset Address (Hex): 30
DSP Memory Management Unit Table 2–39. CAM Entry Register LSB (CAM_L_REG) – Offset Address (hex): 30(Continued) Value at Hardware Value Function Size Access Reset Preserved bit CAM entry not preserved CAM entry preserved Valid bit: CAM entry not valid CAM entry valid 1–0 Section (1 MB) Large pages (64 KB)
Page 105: Global Flush Register (Gflush_Reg) - Offset Address (Hex): 3C
DSP Memory Management Unit Table 2–42. Global Flush Register (GFLUSH_REG) – Offset Address (hex): 3C Value at Hardware Reset Function Size Access 15–1 Reserved Toggle bit. Flush all nonprotected TLB entries when 1 is written. Always 0 when read. Automatically reset. Table 2–43.
Page 106: Ram Entry Register Msb (Read_Ram_H_Reg) - Offset Address (Hex): 4C
DSP Memory Management Unit Table 2–45. CAM Entry Register LSB (CAM_CAM_L_REG) – Offset Address (hex): 48 (Continued) Value at Hardware Value Function Size Access Reset Preserved bit CAM entry not preserved CAM entry preserved Valid bit: CAM entry not valid CAM entry valid 1–0 Section (1 MB)
Page 107: Mpui Simplified Block Diagram
MPU Interface 2.9 MPU Interface The MPU interface (MPUI) allows the TI925T and the system DMA controller to communicate with the DSP and its peripherals via the DSP MPUI port (part of the DSP); see Figure 2–22. The MPUI provides the capability for the TI925T and the system DMA controller to access the full memory space (16M bytes) of the DSP and the DSP peripheral buses, except the private peripherals.
Page 108: Functional Features
MPU Interface 2.9.1 Functional Features The MPUI supports the following features: Four access modes: Single-access mode (SAM) for SARAM, DARAM, memory interface access Single-access mode (SAM) for peripheral bus access Host-only mode (HOM) for SARAM access Host-only mode (HOM) for peripheral bus access An interrupt sent to the TI925T if a time-out occurs Programmable priority scheme (TI925T, DMA, etc.) that must be config- ured during the system boot process...
Page 109: Mpui Registers
MPU Interface In SAM, all the DSP internal memory is accessible by the MPUI interface. If both the DSP and the MPU controllers (TI925T and system DMA) access the same memory at the same time, priority is given to the DSP controllers. The access is synchronized to the internal DSP CPU clock.
Page 110: Control Register (Ctrl)
Byte swap only for APIMEM accesses 15–8 MPUI bus access time out 0xFF 7–4 Division factor of APIF_HNSTROBE. For the OMAP5910 device, this field must be set to 2 (10b) or greater. Settings of 00b or 01b should not be used. 2-58...
Page 111: Control Register (Ctrl_Reg) - Offset: X00
MPU Interface Table 2–49. Control Register (CTRL_REG) – Offset: x00 (Continued) Value at Hardware Value Function Size Access Reset Enables sending IRQ_ABORT interrupt to the MPU when an abort condition is indicated by the MPU port from the DSP system. Disables this interrupt source Reserved Enables the time-out feature.
Page 112: Debug Data Register (Debug_Data) - Offset: X08
MPU Interface Table 2–51. Debug Data Register (DEBUG_DATA) – Offset: x08 Value at Hard- Function Size Access ware Reset 31–0 Value of S_DATA_R is saved when a read access has a size 0xFFFFFFFF mismatch, and S_DATA_W is saved when a write access is aborted or has a size mismatch.
Page 113: Status Register (Status_Reg) - Offset: X10
The STATUS_REG checks the status of the MPU interface during suspend mode (for example, after hitting an emulator breakpoint). The register is for OMAP5910 device chip designers to use for debugging. Table 2–53. Status Register (STATUS_REG) – Offset: x10 Value at...
Page 114: Dsp Status Register (Dsp_Status_Reg) - Offset: X14
MPU Interface Table 2–53. Status Register (STATUS_REG) – Offset: x10 (Continued) Value at Hardware Value Function Size Access Reset Current access mode when ACCESS_DONE = 0 or last access mode when ACCESS_DONE = 1 Table 2–54. DSP Status Register (DSP_STATUS_REG) – Offset: x14 Value at Hardware Value...
Page 115: Dsp Boot Configuration Register (Dsp_Boot_Config) - Offset: X18
DSP devices such as the TMS320C5510, XF is con- nected to a pin and used as an external flag. The OMAP5910 device does not have an XF pin, so this bit is provided to show tha value of the XF bit in the DSP...
Page 116: Dsp Mpui Configuration Register (Dsp_Api_Config) - Offset: X1C
MPU Interface Table 2–56. DSP MPUI Configuration Register (DSP_API_CONFIG) – Offset: x1C Value at Hardware Reset Function Size Access 15–0 APISIZE: Specify which blocks of SARAM are accessible by the 0xFFFF MPUI in HOM (exclusive access). The amount of SARAM is calculated by this formula: API_SIZE/2) * 8K bytes, starting from SARAM0 Table 2–57 decodes SARAM 0 through SARAM 11 on 8K boundaries.
Page 117: Mpu Ti Peripheral Bus Bridge Connections
MPU TI Peripheral Bus Bridges 2.10 MPU TI Peripheral Bus Bridges The MPU TI peripheral bus (TIPB) bridges (see Figure 2–23) connect the TI925T to its peripherals. Two MPU TIPBs, one private and one nonprivate or public, are implemented to reduce access latency and improve system perfor- mance.
Page 118: Access Factor
MPU TI Peripheral Bus Bridges 2.10.2 TIPB Allocation The MPU TIPBs are shared between the MPU and the DMA controller. A bus- allocation module is provided to resolve conflicts and prioritize accesses. The value written in the TIPB_BUS_ALLOC register defines the priority. If the value is 0, the MPU memory interface has priority over the DMA controller.
Page 119: Tipb (Private) Bridge Registers
MPU TI Peripheral Bus Bridges 2.10.4 MPU Posted Write The MPU can perform a posted write. When posted write is enabled inside the ARM_TIPB_CNTL register, data sent by the MPU is buffered in the MPU TIPB and the MPU can keep going to another access. The bridge takes care of the access towards the TIPB;...
Page 120: Tipb (Public) Bridge Registers
MPU TI Peripheral Bus Bridges Table 2–60. TIPB (Public) Bridge Registers Reset Register Name Descriptions Size Address Value TIPB_CNTL TIPB control 16 bits FFFE:D300 0xFF11 TIPB _BUS_ALLOC TIPB bus allocation 16 bits FFFE:D304 0x0009 MPU_TIPB_CNTL MPU TIPB control 16 bits FFFE:D308 0x0000 ENHANCED_TIPB_CNTL...
Page 121: Mpu Tipb Control Register (Mpu_Tipb_Cntl_Reg) - Offset: X08
MPU TI Peripheral Bus Bridges Table 2–63. MPU TIPB Control Register (MPU_TIPB_CNTL_REG) – Offset: x08 Reset Value Description Size Access Value Write buffer is enabled for strobe domain 1. Write buffer is bypassed. Write buffer is enabled for strobe domain 0. Write buffer is bypassed.
Page 122: Data Debug Register Msb (Data_Debug_High) - Offset: X18
MPU TI Peripheral Bus Bridges Table 2–67. Data Debug Register MSB (DATA_DEBUG_HIGH) – Offset: x18 Reset Description Size Access Value 15–0 Bytes 31–16 of data bus from MPU 0xFFFF Table 2–68. Debug Control Signals Register (DEBUG_CNTR_SIG) – Offset: x1C Reset Description Size Access...
Page 123: Little Endian Data Format
Endianism Conversion 2.11 Endianism Conversion Because the TI925T is operated in little endian mode and the DSP is operated in big endian mode, shared data must be converted to their respective formats before any processing is done. Table 2–69 and Table 2–70 illustrate the little and big data formats, respectively.
Page 124: Dsp Data Format
2.11.1 Conversion Through the DSP MMU Swapping buffers are implemented at the boundary between the DSP and the DSP MMU (see Figure 2–24). Assuming that the OMAP5910 system memory is organized in little endian mode, data from and to the DSP is converted as follows: Data is written from the DSP to the system memory.
Page 125: Dsp Endian Conversion, 32-Bit Aligned Data
Endianism Conversion Figure 2–24 shows the endian conversion at the DSP MMU interface bounda- ry. The byte and word swapping is done by decoding the data width and data size, then repacking the data into the appropriate formats. The byte-steering logic provides a mechanism to convert from big to little, little to big, or upper and lower word swap for program code and data accesses.
Page 126: Dsp Endian Conversion, Mpui Port Boundary
Endianism Conversion 2.11.2 Conversion Through the MPUI Swapping buffers are implemented at the boundary between the DSP and the MPUI (See Figure 2–25). The word and byte swapping can be programmed so swapping is individually controlled for MPU memory access and non-MPU memory (peripheral and MPU register).
Page 127: Etm Environment
ETM Environment 2.12 ETM Environment The OMAP5910 device has an embedded trace macrocell (ETM) to provide instruction and data trace capabilities of the TI925T processor. ETM9 in large configuration uses an 8-bit data output. The instruction trace shows the instruction flow of the MPU. The data trace shows the data access results after the MPU executes load and store operations.
Page 128: Trace Signals Multiplexing
ETM Environment The ETM trace signals are multiplexed with the camera interface pins on the OMAP5910 device. The default value upon reset is the camera interface. Refer to Section 6.8, Configuration Module, and Section A.2, I/O Functional Multiplexing, for details on pin multiplexing.
Page 129: Required System For Etm Usage
ETM Environment 2.12.3 Operation Figure 2–27 shows how the OMAP5910 ETM is used in a system setup for capture of trace data. Figure 2–27. Required System for ETM Usage Ethernet Agilent (HP) Trace port analyzer with E5903A 301 TI CCS Ver 2.0 or higher...
Page 130: Additional Reference Materials
ETM Environment 2.12.4 Additional Reference Materials Additional MPU (ARM) ETM related publications of interest include: ETM9 (Rev 0/0a) Technical Reference Manual (ARM DDI 0157B) Trace Port Analysis for ARM ETM Users Guide (Agilent Publications, publication number E5903-97000) Embedded Trace Macrocell (Rev 1) Specification (ARM IHI 0014E) Documentation is also available from Advanced RISC Machines directly via http:\\www.arm.com.
Page 131: Dsp Subsystem
Chapter 3 DSP Subsystem This chapter describes the OMAP5910 multimedia processor DSP subsystem. Topic Page Architecture Overview .........
Page 132: Highlight Of Dsp Subsystem
Various standard memories via the external memory interface (EMIF) Various system peripherals via the TI peripheral bus (TIPB) bridge Figure 3–1 shows the OMAP5910 device with the DSP subsystem high- lighted. Figure 3–2 shows the subsystem and the modules with which it inter- faces.
Page 133: Dsp Subsystem And Modules
Architecture Overview Figure 3–2. DSP Subsystem and Modules DSP private MPU/DSP peripherals DSP subsystem and interfaces shared peripherals Timer DSPTM_CK Mailbox (1 INT) Endianism conversion EMIF Internal memory GPIO I/F WD Timer TMS320C55x buses 1 INT to MPU DSPWD_CK DSP core and/or DSP (1 INT) I-Cache...
Page 134 Architecture Overview The DSP subsystem has the following components: DSP module: TMS320C55x (C55x) DSP CPU core Tightly coupled hardware accelerators—discrete cosine transform/in- verse discrete cosine transform (DCT/IDCT), motion estimation, and half-pixel interpolation Tightly coupled memories and their interfaces—dual-access RAM (DARAM), single-access RAM (SARAM), programmable dynamic ROM (PDROM), instruction cache External memory interface (EMIF) that connects the CPU to external and loosely coupled memories...
Page 135: Dsp Core And Internal Bus Designations
Architecture Overview 3.1.1 DSP Core Figure 3–3 shows the DSP core. Figure 3–3. DSP Core and Internal Bus Designations Private Trace FIFO TIPB bridge C,D,E,F DSP CPU core Shared plus hardware accelerator (DCT/IDCT motion estimation half-pixel interpolation EMIF I-Cache bridge DMA controller 6 channels, 5 ports P,B,C,D,E,F...
Page 136: Tms320C55X Dsp Cpu Overview
TMS320C55x DSP CPU Overview 3.2 TMS320C55x DSP CPU Overview Features for the high-performance, low-power C55x DSP CPU include: Advanced multiple-bus architecture with one internal program memory bus and five internal data buses (three dedicated to reads and two dedicated to writes) Unified program/data memory architecture Dual 17-bit x17-bit multipliers coupled to 40-bit dedicated adders for non- pipelined single-cycle multiply accumulate (MAC) operations...
Page 137: Hardware Acceleration Modules
Advanced low-power complimentary metal-oxide semiconductor (CMOS) process 3.2.2 Hardware Acceleration Modules The OMAP5910 device contains several hardware acceleration modules to improve performance and reduce power consumption for certain computa- tions relating to image and video processing. These coprocessors include: DCT/IDCT accelerator...
Page 138: C55X Dsp Architecture
Data write buses EB, FB (2 x 16) For details on CPU architecture and instruction set, see the following documents: TMS320C55x Technical Overview (SPRU393) TMS320C55x DSP CPU Reference Guide (SPRU371) TMS320C5510 DSP Functional Overview (SPRU312) (only CPU sections apply to the OMAP5910 device)
Page 139: Dsp Memory
DSP Memory 3.3 DSP Memory The DSP subsystem contains four types of tightly coupled memory to enable maximum efficiency of the DSP CPU. Dual-access RAM (DARAM) Single-access RAM (SARAM) Programmable dynamic ROM (PDROM) Configurable instruction cache structure The CPU uses six sets of buses to simultaneously fetch up to 32 bits of pro- gram and read up to 48 bits of data operands from memory (or write up to 32 bits to memory).
Page 140: Dsp Memory Connections
DSP Memory Figure 3–5. DSP Memory Connections 12 blocks of 8K bytes 8 blocks of 8K bytes 1 block of 32K bytes DARAM SARAM PDROM P bus B bus C bus external memory D bus E bus F bus 3.3.1 Internal Memory The DARAM (64K bytes) can support up to two memory accesses in one CPU clock cycle into each RAM block.
Page 141: Instruction Cache
The DSP I-cache on OMAP5910 functions as described in the TMS320C55x DSP Instruction Cache Reference Guide (literature number SPRU576). See this document (I-Cache Type A section) for additional details on the DSP I-cache operation.
Page 142: Dsp I-Cache Input/Output Memory-Mapped Control Registers
DSP Memory Table 3–1 lists the DSP I-Cache I/O-mapped registers. Table 3–1. DSP I-Cache Input/Output Memory-Mapped Control Registers Register Description Access Word Address Reset Value ICGR I-cache global control 0x1400 C006h Reserved Reserved 0x1401 0000h Reserved Reserved 0x1402 0000h ICWC I-cache way control 0x1403 000Dh...
Page 143: Dsp Memory Space
8 blocks * The DMA controller references byte addresses. (Table A) To access control and data registers associated with various OMAP5910 peripherals, the DSP uses 16-bit I/O space. This space is referenced 01_0000 00_8000 by using appropriate I/O access qualifiers with load or store instructions.
Page 144: Peripheral Register Addresses
DSP Memory 3.3.5 Peripheral Register Addresses The DSP CPU and the DMA controller can access several classes of peripheral devices: DSP private peripherals (see Chapter 8) Three general-purpose timers A watchdog timer An interrupt handler MPU/DSP shared peripherals (see Chapter 10) Communications mailbox GPIO control General-purpose UART...
Page 145: Dsp Peripheral Mapping
DSP Memory Table 3–2. DSP Peripheral Mapping † ‡ Start Byte Address (hex) Name Word Address Strobe x000000 TIPB bridge 00000 Strobe 1 x001000 EMIF 00800 Fixed strobe period x001800 00C00 Fixed strobe period x002800 I-cache 01400 Fixed strobe period x005000 TIMER 1 02800...
Page 146: Dma Controller
DMA Controller 3.4 DMA Controller Acting in the background of MPU operation, the DSP DMA controller can: Transfer data among internal memory, external memory, and peripherals residing on the DSP public peripheral bus Transfer data between the MPUI and internal memory Figure 3–7 shows the ports serviced by the DMA controller within the context of the DSP subsystem.
Page 147: Dma And Ports
DMA Controller Figure 3–7. DMA and Ports MPU/DSP DSP 5-Port DMA shared peripherals TMS320C55x DSP Mailbox Endianism conversion EMIF Internal memory GPIO I/F TMS320C55x buses 1 INT to MPU DSP core and/or DSP I-Cache MPU_GPIO_CK Memory Shared Shared Private DARAM TIPB TIPB TIPB...
Page 148: Possible Dma Transfers
Figure 3–8). To arbitrate simultaneous requests, the DMA controller has one programmable service chain that is used by each of the standard ports. The complete operation of the OMAP5910 DSP DMA controller is described in detail in the Direct Memory Access (DMA) Controller section of the TMS320C55x Peripherals Reference Guide (literature number SPRU317).
Page 149: Example Of Dma Configuration
DMA Controller Figure 3–8. Example of DMA Configuration SARAM DARAM EMIF Peripheral bus bridge MPUI P B C D E F P B C D E F P B C D E F IOD IOE SARAM port DARAM port EMIF port Peripheral MPUI port controller...
Page 150: Read/Write Synchronization
DMA Controller 3.4.1.1 DMA Channel Read Synchronization vs. Write Synchronization When a DMA channel is configured for synchronization, the synchronization event is tied to the element read operation or the element write operation depending on the source and destination ports. There are three general cases (see Table 3–4): Case 1: Source port is peripheral;...
Page 151: Dma Controller Configuration Registers
DMA Controller 3.4.2 DMA Controller Configuration Registers Table 3–5 lists the DMA controller configuration registers. Table 3–5. DMA Controller Configuration Registers Register Description Word Address DMA_GCR Global control 0E00h DMA_GTCR Global time-out control 0E01h DMA_GSCR Global software incompatible control 0E02h Channel 0 DMA_CSDP0 Channel 0 source destination parameters...
Page 152 DMA Controller Table 3–5. DMA Controller Configuration Registers (Continued) Register Description Word Address Channel 1 (continued) DMA_CSR1 Channel 1 status 0C23h DMA_CSSA_L1 Channel 1 source start address, lower bits 0C24h DMA_CSSA_U1 Channel 1 source start address, upper bits 0C25h DMA_CDSA_L1 Channel 1 destination start address, lower bits 0C26h DMA_CDSA_U1...
Page 153 DMA Controller Table 3–5. DMA Controller Configuration Registers (Continued) Register Description Word Address Channel 2 (continued) DMA_CSEI2 Channel 2 element index 0C4Bh DMA_CSAC2 Channel 2 source address counter 0C4Ch DMA_CDAC2 Channel 2 destination address counter 0C4Dh DMA_CDEI2 Channel 2 destination element index 0C4Eh DMA_CDFI2 Channel 2 destination frame index...
Page 154 DMA Controller Table 3–5. DMA Controller Configuration Registers (Continued) Register Description Word Address Channel 4 DMA_CSDP4 Channel 4 source destination parameters 0C80h DMA_CCR4 Channel 4 control 0C81h DMA_CICR4 Channel 4 interrupt control 0C82h DMA_CSR4 Channel 4 status 0C83h DMA_CSSA_L4 Channel 4 source start address, lower bits 0C84h DMA_CSSA_U4 Channel 4 source start address, upper bits...
Page 155 DMA Controller Table 3–5. DMA Controller Configuration Registers (Continued) Register Description Word Address Channel 5 (continued) DMA_CEN5 Channel 5 element number 0CA8h DMA_CFN5 Channel 5 frame number 0CA9h DMA_CSFI5 Channel 5 frame index 0CAAh DMA_CSEI5 Channel 5 element index 0CABh DMA_CSAC5 Channel 5 source address counter 0CACh...
Page 156: Dsp Dma Mapping
DSP DMA Event Mapping Table 3–6 defines the mappings of the DMA channel synchronization settings to the different request sources that can be used to create DSP DMA events on OMAP5910. Table 3–6. DSP DMA Mapping DSP DMA Synchronization [4:0]...
Page 157: Tipb Bridge
TIPB Bridge 3.5 TIPB Bridge The TIPB bridge module manages access to peripheral control and data regis- ters by the DSP CPU, DSP DMA controller, and MPUI via two peripheral buses (see Figure 3–9): Private TIPB: peripherals connected here (timers, interrupt handler) cannot be accessed by the MPU via the MPUI.
Page 158: Dsp Subsystem Modules
TIPB Bridge Figure 3–9. DSP Subsystem Modules DSP private MPU/DSP peripherals DSP subsystem and interfaces shared peripherals Timer DSPTM_CK Mailbox (1 INT) Endianism conversion EMIF Internal GPIO I/F memory WD Timer TMS320C55x buses 1 INT to MPU DSPWD_CK DSP core and/or DSP (1 INT) I-Cache...
Page 159: Control Mode Register (Cmr) - Value At Reset Is 0Xfe4D
TIPB Bridge 3.5.1 Control Mode Register (CMR) The CMR indicates shared access mode/host-only mode (SAM/HOM) status of the MPUI and bus error condition status for accesses to the TIPB bridge. It also controls CPU priority versus the MPUI and DMA for accesses to peripherals on the TIPB bridge.
Page 160: Wait States
TIPB Bridge 3) DMA If CPU_Priority = 0, the CPU, MPUI, and DMA accesses to the TIPB bridge are arbitrated in rotating priority fashion. Wait state bits for strb1 and strb2 Strb1 field sets the access rate for the following peripherals: TIPB registers CLKM2 registers Strb2 field sets the access rate for the following peripherals:...
Page 161: Idle Control And Idle Status Registers (Icr And Istr)
TIPB Bridge Time-out[6:0] This field specifies the number of cycles that can elapse before the TIPB returns a bus error condition. The seven-bit field specifies the number of wait states. The time-out period is determined as Time-out = value of time out[6:0] + 2 measured in DSP subsystem master clock cycles The default value is 0x7f (127).
Page 162: Idle Configuration Register (Icr)
TIPB Bridge Table 3–9. Idle Configuration Register (ICR) ICR [15–0] Description DSP Access MPU Access Reset Value 15–8 Reserved (not connected) Read Read Reserved idle domain Read/Write Read Reserved idle domain Read/Write Read EMIF idle domain Read/Write Read DPLL idle domain Read/Write Read Peripherals idle domain...
Page 163: Mpu Interface
MPU Interface 3.6 MPU Interface The MPU interface (MPUI) is a 16-bit parallel port that allows the MPU and the system DMA controller to communicate with the DSP and its peripherals, facili- tating software downloads and data transfers. The MPUI provides the MPU with access to the full memory space of the DSP (16M bytes).
Page 164: Hom/Sam Change Outside Of Reset
MPU Interface the same memory at the same time, priority is given to the DSP controllers. The MPU domain access in SAM is synchronized to the internal DSP CPU clock, which can add access latency for the MPU transfers. HOM provides the MPU with exclusive access to the DSP SARAM or public peripherals, primarily to support high-speed transfers from to DSP during DSP reset or IDLE conditions.
Page 165: St3—Hom_R Bit (Bit 9)
MPU Interface 3.6.3 ST3—HOM_R Bit (Bit 9) The MPUI RAM is the portion of the DSP RAM that is accessible by the MPUI. The HOM_R bit determines/shows whether the MPUI RAM is owned only by the MPUI or shared by the host processor and the C55x DSP: 0: Off The MPUI RAM is shared by the host processor and the DSP.
Page 166: Emif Global Control Register (Emif Gcr)
EMIF 3.7 EMIF The external memory interface (EMIF) is a DSP subsystem module that gives the DSP access to the shared system memory managed by the traffic control- ler. The EMIF interfaces directly to a 32-bit wide system bus. This bus can operate at the CPU clock rate with sustained throughput during burst accesses.
Page 167: Emif Global Reset Register (Emif Grr)
The DSP MMU maps the 16M bytes of the DSP virtual external addresses to anyplace in the 4G-byte address space of the OMAP5910 device. At reset the MMU is disabled and the DSP external memory space is mapped to the first 16M bytes of CS0 system memory.
Page 168: Dsp Subsystem Clocking And Reset Control
OMAP5910. The clock domains in the OMAP5910 platform are synthesized by the DPLL1. The DPLL input clock source is externally supplied from the CLKIN pin.
Page 169: System Operating Details
Two MCSIs—MCSI1 and MCSI2 These peripherals are clocked by the DSPXOR_CK signal, which is a buffered version of the OMAP5910 CLKIN signal. The access rate to these peripherals is configured by strobe 2 control bits in the DSP TIPB CMR register. See Section 3.5.1, Control Mode Register.
Page 170: Dsp Boot Configuration
Register. 3.10.4 Boot Mode for DSP Subsystem The OMAP5910 device contains a bootloader that is a ROM-based utility residing in the DSP subsystem ROM. It consists of a program (code) that facili- tates downloading (bootloading) of DSP code into the DSP subsystem internal memory from either the DSP EMIF interface to the traffic controller or the MPUI interface when it is held in reset by the MPU.
Page 171: Boot Modes
System Operating Details 3.10.4.1 Boot Modes The DSP is reset by two signals: nRESET is a global reset (active low) that resets the DSP subsystem ex- cept for the TIPB interrupt priority encoder, the DSP EMIF configuration registers, and the MPUI port control logic. nMCURESET is a reset signal driven by the MPU (active low).
Page 172: External Memory Boot Table For 16-Bit Boot Download
System Operating Details 3.10.4.2 Boot Table Formats For 16-bit boot download, the boot table in external memory must be in the format shown in Table 3–14. Table 3–14. External Memory Boot Table for 16-Bit Boot Download Word Address (16-Bit Word) Contents Start of External Number of elements of the first section to transfer = N1.
Page 173: External Memory Boot Table For 32-Bit Boot Download
System Operating Details Table 3–14. External Memory Boot Table for 16-Bit Boot Download (Continued) Word Address Contents (16-Bit Word) 2nd word of last section to transfer ..NLth word of last section to transfer 0000h to indicate the end of source program For 32-bit boot download, the the boot table in external memory must be in the format shown in Table 3–15.
Page 174 System Operating Details Table 3-15. External Memory Boot Table for 32-Bit Boot Download (Continued) Word Address Contents (16-bit word) 2nd word of 2nd section to transfer ..N2th word of 2nd section to transfer ..Number of elements of the last section to transfer = NL Most significant word of destination address for the last section.
Page 175: Memory Interface Traffic Controller
Chapter 4 Memory Interface Traffic Controller This chapter describes the OMAP5910 multimedia processor memory interface traffic controller (TC). Topic Page Introduction ..........
Page 176: Tc Block Diagram
OMAP5910 system memory resources (SRAM, SDRAM, flash, ROM, etc.). The TC also manages accesses by the MPU or the USB host. The USB host is an internal OMAP5910 peripheral connected on the local bus, so the TC contributes in managing USB host accesses.
Page 177: Traffic Controller
Introduction Figure 4–2. Traffic Controller To/from To/from MPUI port MPUI Traffic controller SRAM MPU bus Flash SBFlash Slow bus Slow I/F DMA MPUI-DMA Slow port TI peripheral port (public) SDRAM Fast I/F DMA Fast port TIPB System TI peripheral Fast bus port MPU bus (private)
Page 178: Controller Access Mode And Data Access Width
Single and burst access The memories accessed by the TC are separated into two groups: External memory is memory that is not part of the OMAP5910 device. It can be SDRAM, flash, ROM, RAM, etc. External memory is accessed using the external memory interface (EMIF). The TC has two separate memory interfaces to access the external memories.
Page 179 Introduction The TC provides each of the four hosts with: 32-bit single or burst access to memory (must be aligned with a[1-0] = 00) Size adaptation for 8-, 16-, or 32-bit words, with the requirement that address must be aligned on the correct bit boundary. For example, 32-bit access must be aligned on 32-bit boundary, 16-bit access must be aligned on 16-bit boundary, and so forth.
Page 180: Device Types Associated With Chip-Select
† The interface to these memory devices is activated via internal address decoding. There is no external chip select. The OMAP5910 peripherals are mapped on the MPU memory space in two different segments: through STROBE0 (public peripherals) and STROBE1 (private peripherals). Each peripheral has a range of 2K bytes.
Page 181: Mpu Memory Map
Memory Map Table 4–3. MPU Memory Map † Device Name Start Address End Address Size in Bytes Data Access System Memory Address Space External Slow Memory Interface (Flash) FLASH CS0 0000:0000 01FF:FFFF 32M bytes 8/16/32 R/W Reserved 0200:0000 03FF:FFFF FLASH CS1 0400:0000 05FF:FFFF 32M bytes...
Page 182 Memory Map Table 4–3. MPU Memory Map (Continued) † Device Name Start Address End Address Size in Bytes Data Access DSP Shared TIPB Peripherals (Strobe1) UART1 E101:0000 E101:07FF 2K bytes 8 R/W UART2 E101:0800 E101:0FFF 2K bytes 8 R/W Reserved E101:1000 E101:17FF 2K bytes...
Page 183 Memory Map Table 4–3. MPU Memory Map (Continued) † Device Name Start Address End Address Size in Bytes Data Access MPU Public TIPB Peripherals (Strobe 0) (continued) USB function FFFB:4000 FFFB:47FF 2K bytes 16 R/W FFFB:4800 FFFB:4FFF 2K bytes 8 R/W MPUIO FFFB:5000 FFFB:57FF...
Page 184 MPU Private TIPB Peripherals (Strobe 1) MPU level 2 interrupt handler FFFE:0000 FFFE:07FF 2K bytes 32 R/W ULPD power management FFFE:0800 FFFE:0FFF 2K bytes 16 R/W OMAP5910 configuration FFFE:1000 FFFE:17FF 2K bytes 32 R/W Die ID FFFE:1800 FFFE:1FFF 2K bytes 32 R/W Reserved...
Page 185 Memory Map Table 4–3. MPU Memory Map (Continued) † Device Name Start Address End Address Size in Bytes Data Access MPU Private TIPB Peripherals (Strobe 1) (Continued) Reserved FFFE:D100 FFFE:D1FF 256 bytes DSP MMU FFFE:D200 FFFE:D2FF 256 bytes 32 R/W MPU public TIPB bridge FFFE:D300 FFFE:D3FF...
Page 186: Memory Interfaces
IMIF Priority Handler This memory interface has two software-selectable priority algorithms for resolving simultaneous access requests: least recently used and dynamic priority. The priority scheme is shared with the EMIFS and EMIFF and is set OMAP5910 configuration registers (bit LRU_SEL FUNC_MUX_CTRL_0).
Page 187: External Memory Interface Slow Signal List
Active-low chip-select for device FLASH.CS3 – Active-low chip-select for device † FLASH.CS2 and FLASH.BAA are multiplexed on the same device pin. Pin function is selected using the OMAP5910 configu- ration register, FUNC_MUX_CRTL_0. The FLASH.CS2 functionality is default. Memory Interface Traffic Controller 4-13...
Page 188 FLASH.BE 3 – 0 External byte enable † FLASH.CS2 and FLASH.BAA are multiplexed on the same device pin. Pin function is selected using the OMAP5910 configu- ration register, FUNC_MUX_CRTL_0. The FLASH.CS2 functionality is default. Note: OMAP5910 multiplexes the FLASH.CS2 and FLASH.BAA pin functionality to the same device pin.
Page 189 Memory Interfaces At reset, all requestors are initially in the low-priority queue and the time-out registers are set to minimum value for each requestor. You must program these registers before using dynamic priority. The low-priority queue order is: Local bus DMA (all channels including LCD) The high-priority queue order is: DMA transfer involving LCD channel...
Page 190 Memory Interfaces The following operations are also supported for burst flash devices: Synchronous burst read mode (for Intel and AMD flashes) An additional read mode is provided that supports burst read on page mode ROM devices. Figure 4–3 through Figure 4–7 show the external timing of the protocols used by the EMIF slow interface.
Page 191: Fclkdiv Settings And Resulting Emifs Reference Clock
In synchronous modes a selectable retiming feature enables read data to be latched by a delayed EMIFS reference clock. The retiming feature accounts for delays through the OMAP5910 input/output pins by feeding back FLASH.CLK to offer optimum data and clock alignment. You can select the re- timing mode using the RT bit in the EMIFS chip-select configuration registers.
Page 192: Asynchronous 16-Bit Read Operation On A 16-Bit Width Device
Memory Interfaces 4.3.2.5 Asynchronous Read Operation Asynchronous read mode is selected by programming the RDMODE bit field to 000 in the corresponding EMIF slow chip-select configuration register. This is the default mode at reset. The following characteristics describe asynchronous read mode operation. The chip-select pulse width depends on the RDWST bit field of the EMIFS chip-select configuration register.
Page 193 Memory Interfaces 4.3.2.6 Asynchronous Page Mode Read Operation The asynchronous read operation (page mode) is similar to the asynchronous read, except that the number of wait states is different between the first access and the subsequent accesses within the page. This mode of operation is selected by programming the following fields of the EMIF slow chip-select configuration registers (see Table 4–13, EMIF Slow Chip-Select Configuration Registers).
Page 194: Asynchronous Page Mode 8X16-Bit Read Operation On A 16-Bit Width Device
Memory Interfaces Figure 4–4. Asynchronous Page Mode 8x16-Bit Read Operation on a 16-Bit Width Device (8 Words per Page) TC Clock (internal) EMIFS Ref (internal) FLASH.CLK N cycles FLASH.CS_[X] FLASH.ADV P cycles Addr4 FLASH.A(24:1) Add0 Add1 Add2 Add3 Add5 Add6 Add7 FLASH.D(15:0) FLASH.OE...
Page 195 The synchronous read mode is selected for each device by setting the RDMODE configuration bit field to 100. In this mode of operation, FLASH.CLK is driven on the OMAP5910 device pin. Both AMD burst flash and Inter burst flash have three modes of operation:...
Page 196: Synchronous Burst Read With
Memory Interfaces Figure 4–6. Synchronous Burst Read With Page Alignment Synchronous Burst Read Operation (1/2) TC clock FLASH.CLK (FDIV=1) (RDWST+1)xFDIV TC clock cycles 1 TC clock cycles FLASH.CLK (FDIV=2) (RDWST+1)xFDIV TC clock cycles 2 TC clock cycles FLASH.CLK (FDIV=4) (RDWST+1)xFDIV TC clock cycles 4 TC clock cycles FLASH.CLK (RDWST+1)xFDIV TC...
Page 197: Asynchronous Write With We Operation
Memory Interfaces 4.3.2.8 Asynchronous Write With WE Operation The asynchronous write is used for both file flash and burst flash devices. Figure 4–7 shows the timing diagram. Burst write operation is not supported. Figure 4–7. Asynchronous Write With WE Operation FLASH.CLK Î...
Page 198 EMIFS Not-Ready Functionality The EMIFS interface includes a feature that allows an external device to assert a not-ready signal via the OMAP5910 FLASH.RDY pin. Two modes of not- ready are available: classic and dynamic. In either mode, if FLASH.RDY is low, the external device is not ready.
Page 199: External Memory Interface Fast Signal List
Memory Interfaces mode is recommended only for 16-bit accesses since the OMAP5910 EMIFS keeps chip-select and write enable active between the two accesses gener- ated by one 32-bit access to EMIFS. While nothing prevents the use of 32-bit accesses in DPRAM interface mode, avoid it if address must be known valid while write enable is active.
Page 200 Memory Interfaces Dynamic priority Dynamic priority uses high- and low-priority queues. Each requestor, except the MPU, has a time-out register allocated to it (see Time-Out Registers in Section 4.4). These registers hold the number of clock cycles that a low-priority queue request has to wait before it is moved from the low-priority queue to the high-priority queue.
Page 201: Possible Sdram Configurations
The self-refresh mode (idle) and autorefresh (normal operation) Automatic generation of MRS and EMRS commands to the SDRAM by writing to a mirror configuration register within the OMAP5910 device Burst sizes of 1x8, 1x16, 1x32, and 4x32 for all accesses and 8x16 burst access for LCD.
Page 202 To make SDRAM memory accessible, its internal mode register must first be configured. The MRS register contains the protocol information used to com- municate with the OMAP5910 device (burst size, latency, write burst, etc.). The EMRS register enables certain low-power characteristics for the SDRAM.
Page 203 SDRAM Self-Refresh Protection The traffic controller idle mode is entered after an internal request and acknowledge protocol with the OMAP5910 clock generator and system reset module. In idle mode, the traffic controller clock is stopped. If the clock remains idle for more than 64 milliseconds and the SDRAM was not entered into self refresh mode, SDRAM data corruption results.
Page 204 Memory Interfaces Caution: Self-Refresh Mode When the EMIFF SDRAM is in self-refresh mode, the EMIFF does not respond to TIPB requests including MRS writes. To respond, the SLFR bit must be cleared by firmware. Writes to TC registers which would normally cause EMIFF to perform an action have no effect while EMIFF is in self-refresh mode.
Page 205: Sdram Write Single 32-Bit Word With Burst Stop
Memory Interfaces Figure 4–8. SDRAM Write Single 32-Bit Word With Burst Stop ACTV0 WRITE STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 Ignored C0+1 C0+2 CURRENT_COL C0+1 CURRENT_SIZE DVALID SAVE_ADD LAST_DATE Note: WRITE (burst reduced to 2) is interrupted by a STOP command because no new request is pending. Memory Interface Traffic Controller 4-31...
Page 206: Sdram Write Single 16-Bit Half-Word With Burst Stop
Memory Interfaces Figure 4–9. SDRAM Write Single 16-Bit Half-Word With Burst Stop ACTV0 WRITE STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 Ignored C0+1 CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE Note: WRITE (burst reduced to 1) is interrupted by a STOP command because no new request is pending. 4-32...
Page 207: Sdram Write Single 16-Bit Half-Word Followed By Write Burst
Memory Interfaces Figure 4–10. SDRAM Write Single 16-Bit Half-Word Followed by Write Burst 8 ACTV0 WRITE WRITE STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B1/C1 C0+1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 C1+8 CURRENT_COL C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 Output column counter CURRENT_SIZE DVALID...
Page 208: Sdram Read Single 16-Bit Half-Word With Burst Stop
Memory Interfaces Figure 4–11.SDRAM Read Single 16-Bit Half-Word With Burst Stop ACTV0 READ STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 L = 3 C0+1 CURRENT_COL CURRENT_SIZE DVALID SAVE_ADD LAST_DATE Note: READ (burst reduced to 1) is interrupted by a STOP command because no new request is pending. 4-34...
Page 209: Sdram Read Single 16-Bit Half-Word Followed By Read Burst 8 Half-Word
Memory Interfaces Figure 4–12. SDRAM Read Single 16-Bit Half-Word Followed by Read Burst 8 Half-Word ACTV0 READ READ STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B1/C1 L = 3 C0+1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 C1+8 CURRENT_COL C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 Output column counter CURRENT_SIZE...
Page 210: Sdram Write Burst 32-Bit Word Followed By Read Burst 8 Half-Word
Memory Interfaces Figure 4–13. SDRAM Write Burst 32-Bit Word Followed by Read Burst 8 Half-Word ACTV0 WRITE READ STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B1/C1 L = 3 Ignored C0+1 C1+2 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 C1+8 CURRENT_COL C0+1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6...
Page 211: Sdram Single Half-Word Followed By A Read Burst 6 Half-Words
Memory Interfaces Figure 4–14. SDRAM Single Half-Word Followed by a Read Burst 6 Half-Words ACTV0 WRITE STOP ACTV0 WRIT STOP ACCESS_REG ACCESS_GRANT t rc = 9 COMMAND t ras = 5 ADDRESS B0/R0 B0/C0 B0/R0 B0/R5 C0+1 C5+1 C5+2 C5+3 C5+4 C5+5 C5+6 CURRENT_COL C5+1 C5+2 C5+3 C5+4...
Page 212: Sdram Read Burst 4 Half-Words Followed By A Write Burst 3 Half-Words
Memory Interfaces Figure 4–15. SDRAM Read Burst 4 Half-Words Followed by a Write Burst 3 Half-Words STOP ACTV0 READ WRITE STOP ACCESS_REG ACCESS_GRANT COMMAND ADDRESS B0/R0 B0/C0 B1/C1 L = 3 C0+1 C0+2 C0+3 C0+4 C1+1 C1+2 C1+3 CURRENT_COL C0+1 C0+2 C0+3 C1+5 C1+6...
Page 213: Sdram Read Single Half-Word Followed By A Write Byte
Memory Interfaces Figure 4–16. SDRAM Read Single Half-Word Followed by a Write Byte ACTV0 READ ACTV0 WRIT STOP ACCESS_REG ACCESS_GRANT COMMAND t ras = 4 ADDRESS B0/R0 B0/C0 B0/R0 B0/R5 B0/C5 L = 3 t rc = 9 DQMU DQMx DQML C0+1 C5+1...
Page 214: Sdram Write Single Followed By Write Burst 6 On The Same Bank And Different Page
Memory Interfaces Figure 4–17. SDRAM Write Single Followed by Write Burst 6 on the Same Bank and Different Page ACTV0 WRIT STOP ACTV0 WRIT STOP ACCESS_REG ACCESS_GRANT t rc = 9 COMMAND t ras = 5 ADDRESS B0/R0 B0/C0 B0/R0 B0/R5 C0+1 C5+1 C5+2 C5+3 C5+4 C5+5...
Page 215 ACTV0 READ STOP ACTV0 READ STOP READ DEAC ACCESS_REQ ACCESS_GRANT COMMAND B1/R1 ADDRESS B0/R0 B0/C0 B1/C1 B1/R1 B1/00 L = 3 Detection of new row DQMx C0+1 C1+1 C1+2 = 00 C1+3 C1+4 C1+5 C1+6 C1+7 C1+8 CURRENT_COL C1+1 C1+2 = 00 C1+3 C1+4 C1+5...
Page 216: Traffic Controller Registers
Traffic Controller Memory Interface Registers 4.4 Traffic Controller Memory Interface Registers OMAP5910 traffic controller base address is 0xFFFE:CC00. Table 4–8 lists the traffic controller registers. Table 4–9 through Table 4–27 describe the register bits. The EMIF slow interface configuration register provides access to EMIFS boot, operation, and power-down options (see Table 4–12).
Page 217: Imif Priority Register (Imif_Prio)
Traffic Controller Memory Interface Registers Table 4–8. Traffic Controller Registers (Continued) Name Description Size Address Reset Value ENDIANISM Endianism 32 bits 0xFFFE:CC34 0x0000 0000 Location not used 0xFFFE:CC38 EMIFF_SDRAM_CONFIG_2 EMIF fast interface SDRAM 32 bits 0xFFFE:CC3C 0x0000 0003 configuration register 2 EMIFS_CFG_DYN_WAIT EMIF slow wait-state 32 bits...
Page 218: Emif Slow Interface Configuration Register (Emifs_Config_Reg)
Traffic Controller Memory Interface Registers Table 4–12. EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG) Reset Field Value Description Access Value 31–5 Reserved Read is undefined. Writes must be zero. All 0 Ready signal. This bit is a copy of the FLASH.RDY input pin as sampled by TC clock.
Page 219: Emif Slow Chip-Select Configuration Registers
Specifies EMIFS data bus width. 16-bit bus. This is the appropriate setting for OMAP5910. Reserved. Do not use this setting on OMAP5910. (BW bit reset value depends on the chip-select: For CS0 and CS3, BW = 0; For CS1 and CS2, BW = 1.
Page 220: (Emifs_Cs0_Config
Traffic Controller Memory Interface Registers Table 4–13. EMIF Slow Chip-Select Configuration Registers (EMIFS_CS0_CONFIG...EMIFS_CS3_CONFIG) (Continued) Reset Field Value Description Access Value RDWST Number of wait states for asynchronous read 1111 operation (see Table 4–15). Number of inserted clock cycles in protocol (value matches the value programmed in Intel flash devices).
Page 221: Wait Cycles Insertion
Traffic Controller Memory Interface Registers Table 4–15. Wait Cycles Insertion RDWST Number of Cycles Inserted There is no automatic hardware adjustment of the programmed latencies when the system clock frequency changes. The following restrictions apply when synchronous burst read Intel protocol is selected: Only continuous burst mode is supported Only sequential data access order is supported...
Page 222: Emif Fast Interface Sdram Configuration Register
Traffic Controller Memory Interface Registers Table 4–16. EMIF Fast Interface SDRAM Configuration Register 1 (EMIFF_SDRAM_CONFIG) (Continued) Reset Field Value Description Access Value SDRAM power-down enable. Controls power-down state of SDRAM interface: SDRAM interface is not powered down. SDRAM interface is powered down. PWD is one of the prerequisites to meet TC idle.
Page 223: Sdram Internal Organization
Data is single buffered with the return clock from SDRAM. Data from SDRAM is double buffered. Data is first clocked on return clock from SDRAM, then with the OMAP5910 internal SDRAM clock. SLRF When set, places the SDRAM in self-refresh mode. Mode is automatically exited upon the generation of any SDRAM access.
Page 224: Frequency Range
Traffic Controller Memory Interface Registers Table 4–17. SDRAM Internal Organization (Continued) Memory Size Number Of Register Value (M Bits) Size Of Data Bus Banks † 1010 1011 † 1100 1101 † 1110 1111 † Unavailable bank number (not supported). Do not use this setting. Note: Reset value = 0x0h.
Page 225: Sdram Timing Requirements
Traffic Controller Memory Interface Registers Table 4–19. SDRAM Timing Requirements Meeting this Timing With SDRAM.CLK = SDRAM Timing 60 MHz (16.7 ns ac Parameters Requirements (ns) Period) (trwl) – – † Write is never interrupted by precharge command directly. ‡ Neither read or write with autoprecharge is supported. For 60 MHz, timing can be met by using the SDF1 timing configuration.
Page 226: Emif Fast Interface Sdram Mrs Register—Default (Emiff_Mrs)
EMIFF operates, but rather a setting for the SDRAM MRS register.) Note: When the CONF_MOD_EMRS_CTRL bit field (bit 13) of the OMAP5910 control register (MOD_CONF_CTRL_0) is set, the device reconfigures bank settings to write out the EMIFF_MRS register as EMRS commands (see Table 4–21).
Page 227: Emif Fast Interface Sdram Mrs Register—Emrs Mode (Emiff_Mrs)
Traffic Controller Memory Interface Registers Table 4–21. EMIF Fast Interface SDRAM MRS Register—EMRS Mode (EMIFF_MRS) Reset Field Value Description Access Value 31–5 Reserved Read is undefined. Writes must be zero. Note 1 4–3 TCSR SDRAM EMRS register temperature compensated self-refresh setting: Note 1 70 degrees Celsius maximum case temperature 45 degrees Celsius maximum case temperature...
Page 228: Time-Out 1 Register (Timeout1)
Traffic Controller Memory Interface Registers The three time-out registers store the number of clock cycles before DSP, DMA, LCD, LB requests are made high-priority in dynamic priority scheme for the TC (see Table 4–22 through Table 4–24). Table 4–22. Time-Out 1 Register (TIMEOUT1) Reset Field Description...
Page 229: Endianism Register (Endianism)
Traffic Controller Memory Interface Registers The endianism register (ENDIANISM) is used to control endianism conversion in the DSP memory management unit endianism block. Table 4–25. Endianism Register (ENDIANISM) Reset Field Value Description Access Value 31–2 Reserved Read is undefined. Writes must be zero. All 0 SWAP Byte swap (8 bits)
Page 230: Emif Slow Wait State Configuration (Emifs_Cfg_Dyn_Wait)
Traffic Controller Memory Interface Registers Table 4–27. EMIF Slow Wait State Configuration (EMIFS_CFG_DYN_WAIT) Reset Field Value Description Access Value 31–4 Reserved Read is undefined. Writes must be zero. All 0 DYNW_CS3 Specifies function of FLASH.RDY for CS3. Enable classic not-ready for EMIFS CS3. Enable dynamic not-ready for EMIFS CS3.
Page 231: Interfacing Memories With The Omap5910 Device
4.5 Interfacing Memories With the OMAP5910 Device This section provides two examples of how to connect memories to the OMAP5910 device. Many scenarios can be considered using different kinds of memories. For flash memories, Intel and Hitachi products are used. For SDRAM and SRAM, Hitachi and Toshiba products are used, respectively.
Page 232: External Memory Interconnection Using Intel Flash Memory
Interfacing Memories With the OMAP5910 Device Figure 4–19. External Memory Interconnection Using Intel Flash Memory OMAP5910 SDRAM GND fixed HM52Y64165F SDRAM_CLK (Hitachi) SDRAM.CKE 2.5 V–2.8 V SDRAM.RAS SDRAM.CAS SDRAM.WE SDRAM.DQMU DQMU SDRAM.DQML DQML SDRAM.D[15:0] DQ[15:0] SDRAM.BA[1:0] BA[1:0] SDRAM.A[11:0] A[11:0] SDRAM.A[12]...
Page 233: External Memory Interconnection Using Hitachi Flash Memory
Interfacing Memories With the OMAP5910 Device Figure 4–20. External Memory Interconnection Using Hitachi Flash Memory OMAP5910 SDRAM GND Fixed HM52Y64165F SDRAM_CLK (Hitachi) SDRAM.CKE 2.5 V–2.8 V SDRAM.RAS SDRAM.CAS SDRAM.WE SDRAM.DQMU DQMU DQML SDRAM.DQML SDRAM.D[15:0] DQ[15:0] SDRAM.BA[1:0] BA[1:0] A[11:0] SDRAM.A[11:0] SDRAM.A[12]...
Page 234: System Dma Controller
Chapter 5 System DMA Controller This chapter describes the system DMA controller for the OMAP5910 multimedia processor. Topic Page Introduction ..........
Page 235: Highlight Of Dma Controller
MPU operation. It is designed to off-load the block data transfer function from the MPU processor. Figure 5–1 shows the OMAP5910 device with the DMA controller highlighted. Figure 5–2 shows the controller in more detail.
Page 236: Dma Controller Block Diagram
Introduction Figure 5–2. DMA Controller Block Diagram Addr To interleaver Local Port DOUT Local Interleaver Request Addr Allocator EMIFS Port DOUT EMIFS FIFO 0 Interleaver Configuration register Dma _nreq bank 0 (5:0) R/W Unit 0 Interrupt generator Addr EMIFF Port DOUT EMIFF Interleaver...
Page 237 Introduction Transfers are made through a physical channel that can be thought of as a pipe that connects a source and a destination for the duration of a transfer. Data flows through this pipe from the source to the destination. After the transfer is completed, the pipe (channel) can be used to perform other data transfers that involve the same or other sources and destinations.
Page 238 Introduction The system DMA controller is controlled by the MPU (via the TIPB). The DMA controller meets the high-rate-flow requirements of the multichannel applica- tions used by wireless base stations. The system DMA controller is designed for low-power operation. Its clock can be automatically disabled as required.
Page 239 Introduction Memory-to-memory transfer granularity of 8, 16, and 32 bits. Only the number of programmed bytes is transferred; that is, there are no trailing or dirty bytes at the end of transfer. TIPB-to-memory transfer: When performing DMA transfers from a TIPB peripheral, is it ideal that the peripheral FIFO size be 16 bytes, which corresponds to the DMA channel FIFO size.
Page 240: Possible Data Transfers
Introduction Table 5–1. Possible Data Transfers Destinations EMIFS EMIFF IMIF TIPB MPUI Local Bus vs. Sources EMIFS bus EMIFF bus IMIF bus TIPB MPUI Local bus Table 5–2. Possible Transfer Sizes and Types Destination: Destination: Destination: Destination: Destination: Destination: 16-Bit 32-Bit 8-Bit TIPB 8-Bit Non-TIPB...
Page 241: System Dma External Connections
External Connections 5.2 External Connections The system DMA controller is interconnected with other OMAP5910 components as shown in Figure 5–3. Figure 5–3. System DMA External Connections EMIFS DMA_IT_NF(5–0) EMIFS port IMIF IMIF port EMIFF EMIFF port Local System DMA Local bus...
Page 242: Time-Sharing On A Dma Port
Generic Channels 5.3 Generic Channels This section discusses the following generic channel topics: Transfers Addressing modes Data packing and bursting Data alignment Constraint on channel configuration parameters Endianism Interrupt generation Memory space protection 5.3.1 Transfers 5.3.1.1 Transfer Sources and Destination Each DMA channel can be configured independently from other channels.
Page 243: Basic Flow Of Dma Transfer
Generic Channels 5.3.1.2 Transfer Control Figure 5–5. Basic Flow of DMA Transfer MPU loads the transfer configuration registers. DMA channel Interrupt generated IDLE No request DMA request Synchronized request? Hardware signal OK? Transfer one element/frame Transfer completed 5-10...
Page 244 Generic Channels 5.3.1.3 Transfer Start There are two ways to start a DMA transfer: Software start (software request): After setting up the configuration regis- ters of a DMA channel, the processor activates the transfer in this channel by writing the DMA_CCR.en bit of this channel. The transfer immediately starts.
Page 245 Generic Channels 5.3.1.5 Autoinitialization A DMA channel (synchronized or not) can operate in two modes. Single transfer mode In this mode, a channel stops when the current transfer finishes Autoinitialization mode In this mode, a channel loads a new configuration and automatically restarts a new transfer when the current one finishes.
Page 246: Autoinitialization Configuration Bits Summary
Generic Channels To avoid the reload of a configuration when the MPU programs the channel, the MPU can use the autoinitialization bits of the DMA_CCR register, which are described in Table 5–3. Table 5–3. Autoinitialization Configuration Bits Summary AUTOINIT END_PROG REPEAT Autoinitialization Behavior No autoinitialization...
Page 247: Memory Representation
Generic Channels Figure 5–6. Memory Representation Byte @ addr 00 Byte @ 01 Element size Element n Byte @ 02 (Can be 1, 2, 4. Here: Element size = 4) Byte @ 03 Element index (address increments by this Byte @ 04 value after an element) Frame n Byte @ 05...
Page 248 Generic Channels FN is the number of frames in the block, 1 ≤ FN ≤ 65535. EN is the number of elements per frame, 1 ≤ EN ≤ 65535. ES is the number of bytes per element, ES ∈ {1, 2, 4}. An element can be: 8-bit scalar data, s8 16-bit scalar data, s16...
Page 249 Generic Channels 5.3.2.2 Post-Incremented Addressing Mode Address is always incremented by 1. a(0) =SA a(i) =a(i – 1) + 1, 1 ≤ i ≤ BS –1 where: a(i) is the address of the byte number i within the transfer. SA is the start address of the transfer. BS is the block size in bytes.
Page 250: Data Packing And Bursting
Generic Channels a(0) = SA a(i) = a(i – 1) + 1 if (i mod ES) ≠ 0 and (i mod FS) ≠ 0, 1 ≤ i ≤ BS – 1 a(i) = a(i – 1) + EI if (i mod ES) = 0 and (i mod FS) ≠ 0, 1 ≤ i ≤ ΒS – 1 a(i) = a(i –...
Page 251: Packing And Splitting Summary
Generic Channels Table 5–4. Packing and Splitting Summary Data Type Port Access Capability Packing/Splitting – pack 2 x s8 => 16 pack 4 x s8 => 32 split s16 => 2 x 8 – pack 2x s16 => 32 split s32 => 4 x 8 split s32 =>...
Page 252 Generic Channels A transfer to/from a DMA port with 32-bit only access capability must be set up as follows: Element size is a multiple of four. Start address is aligned on a 32-bit word. If frame index is used, it must always produce addresses aligned on a 32-bit word.
Page 253: Data Block To Transfer
Generic Channels Table 5–5. Data Block to Transfer Address Byte 0 Byte 1 Byte 2 Byte 3 Element 1, 1 Element 1, 2 Element 1, 3 Element 1, 4 Element 1, 5 Element 2, 1 Element 2, 2 Element 2, 3 Element 2, 4 Element 2, 5 The computed addresses and access types are as identified in Table 5–6.
Page 254: Data/Address Alignment
Generic Channels 5.3.4 Data/Address Alignment During a transfer, all the addresses computed by the DMA must be aligned on the type of data transferred: If the data type is s8 (8 bits scalar data), addresses can have any value. If the data type is s16 (16 bits scalar data), addresses must be aligned on 16-bit word boundary (the least bit of the address is always 0).
Page 255: Endianism Adaptation On Transferred Data
The MSB of the word is placed on the LSB of the bus. The internal FIFOs of the system DMA are big endian. All system DMA ports are treated as little endian on OMAP5910. Therefore, the system DMA con- tains adaptation logic to convert incoming data to big endian and outgoing data back to little endian.
Page 256: Interrupt Generation
Generic Channels 5.3.7 Interrupt Generation Each DMA physical channel can generate an interrupt to the processor to reflect the transfer status. Each DMA physical channel has a dedicated inter- rupt line to the processor. All the DMA interrupts are level interrupts. For every DMA logical channel, the following interrupt sources can be programmed: End of block: The last byte of the transfer has been written in destination.
Page 257: Data Read Format-Two Shared Physical Channels
Generic Channels The system DMA has nine physical channels; each has the capability to gener- ate interrupts. The DMA has seven interrupt lines, some of which are shared by two physical channels. Each of these seven interrupt lines is routed as an interrupt input on the MPU level2 interrupt handler.
Page 258: Data Read Format-One Physical Channel
Generic Channels Figure 5–9. Data Read Format—One Physical Channel Physical channel 3 status register 5.3.8 Memory Space Protection To set up a transfer, the software specifies: source port with an address that must hit in the source port memory space. A destination port with an address that must hit in the destination port memory space.
Page 259: Lcd Dedicated Channel
LCD Dedicated Channel 5.4 LCD Dedicated Channel The LCD channel transfers 16-bit data to the LCD controller from a video frame buffer stored in memory. 5.4.1 Functional Description The memory source for the LCD dedicated transfer can be either IMIF or EMIFF.
Page 260: Addressing Units
LCD Dedicated Channel the DMA to the LCD FIFO, the maximum burst length is set to eight. Only near frame boundaries, in case of nonmultiple frames, are single transfers started; otherwise, all requests to the source memory are in 8 x 16 burst requests. The LCD channel priority bit is fixed high (hard-coded LCD channel constant parameter).
Page 261: Lcd Channel Usage Restrictions
LCD Dedicated Channel BF2 is bottom address for frame 2. TF1 is top address for frame 1. TF2 is top address for frame 2. DFM is the dual-frame mode. In other words, the next address is always the current address + 2 unless the frame boundaries (inclusive) have been reached (address is a byte address;...
Page 262: Emif To Lcd Register Settings-One Frame
LCD Dedicated Channel to continue until the LCD enable signal (dma_lcd_en) is disabled one time (LCDEN = 0). This mechanism is provided to avoid having dummy high-priority requests to the ports because the LCD channel’s frame data flow has been corrupted.
Page 263: Lcd One Frame Mode Transfer Scheme
LCD Dedicated Channel The transfer runs, and an interruption is generated at the end of the frame. Figure 5–11.LCD One Frame Mode Transfer Scheme SDRAM lcd_top_frame1 0x0B 0000 Video frame controller 0x0B 00DE lcd_bot_frame1 When an interrupt occurs, read the DMA_LCD_CTRL register to find the source of the interrupt.
Page 264: Lcd Dual-Frame Mode Transfer Scheme
LCD Dedicated Channel Table 5–8. IMIF LCD Register Settings—Two Frames (Continued) DMA_LCD_CTRL Register Settings DMA_LCD_TOP_F1_L 0x0000 DMA_LCD_BOT_F1_U 0x000B DMA_LCD_BOT_F1_L 0x00DE DMA_LCD_TOP_F2_U 0x000C DMA_LCD_TOP_F2_L 0x0000 DMA_LCD_BOT_F2_U 0x000C DMA_LCD_BOT_F2_L 0x00DE The transfer starts when the enable (hardware) signal from the LCD controller is asserted high.
Page 265: Dma Request Mapping
DMA Request Mapping 5.5 DMA Request Mapping Table 5–9 shows the DMA request mapping for the OMAP5910 device. Table 5–9. DMA Request Mapping MPU System DMA Requests MPU System DMA MCSI1 TX DMA_REQ_01 MCSI1 RX DMA_REQ_02 C RX DMA_REQ_03 C TX...
Page 266 DMA Request Mapping Table 5–9. DMA Request Mapping (Continued) MPU System DMA Requests MPU System DMA Reserved DMA_REQ_025 USB function RX0 DMA_REQ_026 USB function RX1 DMA_REQ_027 USB function RX2 DMA_REQ_028 USB function TX0 DMA_REQ_029 USB function TX1 DMA_REQ_030 USB function TX2 DMA_REQ_031 System DMA Controller 5-33...
Page 267: Registers
Registers 5.6 Registers Table 5–10 describes the DMA controller registers. Note: The DMA control registers are part of a register superset for multiple OMAP- based devices. They are defined for a 16-port, 16-channel DMA controller. Thus as generic as possible a register mapping is provided, so some regis- ters may appear to be almost empty.
Page 268 Registers Table 5–10. DMA Controller Registers (Continued) Size Name Description Address Reset Value (Bits) DMA_CCR_CH1 Channel 1 control 0xFFFED842 0x0000 DMA_CICR_CH1 Channel 1 interrupt control 0xFFFED844 0x0003 DMA_CSR_CH1 Channel 1 status 0xFFFED846 0x0000 DMA_CSSA_L_CH1 Channel 1 source start address 0xFFFED848 lower bits DMA_CSSA_U_CH1 Channel 1 source start address...
Page 269 Registers Table 5–10. DMA Controller Registers (Continued) Size Name Description Address Reset Value (Bits) DMA_CFN_CH2 Channel 2 frame number 0xFFFED892 DMA_CFI_CH2 Channel 2 frame index 0xFFFED894 DMA_CEI_CH2 Channel 2 element index 0xFFFED896 DMA_CPC_CH2 Channel 2 channel progress counter 0xFFFED898 DMA_CSDP_CH3 Channel 3 source destination 0xFFFED8C0 0x0000...
Page 270 Registers Table 5–10. DMA Controller Registers (Continued) Size Name Description Address Reset Value (Bits) DMA_CSSA_U_CH4 Channel 4 source start address 0xFFFED90A upper bits DMA_CDSA_L_CH4 Channel 4 destination start address 0xFFFED90C lower bits DMA_CDSA_U_CH4 Channel 4 destination start address 0xFFFED90E upper bit DMA_CEN_CH4 Channel 4 element number 0xFFFED910...
Page 271 Registers Table 5–10. DMA Controller Registers (Continued) Size Name Description Address Reset Value (Bits) DMA_CSDP_CH6 Channel 6 source destination 0xFFFED980 0x0000 parameters DMA_CCR_CH6 Channel 6 control 0xFFFED982 0x0000 DMA_CICR_CH6 Channel 6 interrupt control 0xFFFED984 0x0003 DMA_CSR_CH6 Channel 6 status 0xFFFED986 0x0000 DMA_CSSA_L_CH6 Channel 6 source start address...
Page 272 Registers Table 5–10. DMA Controller Registers (Continued) Size Name Description Address Reset Value (Bits) DMA_CFI_CH7 Channel 7 frame index 0xFFFED9D4 DMA_CEI_CH7 Channel 7 element frame 0xFFFED9D6 DMA_CPC_CH7 Channel 7 channel progress counter 0xFFFED9D8 DMA_CSDP_CH8 Channel 8 source destination 0xFFFEDA00 0x0000 parameters DMA_CCR_CH8 Channel 8 control...
Page 273: Dma Global Control Register (Dma_Gcr)
Registers Table 5–10. DMA Controller Registers (Continued) Size Name Description Address Reset Value (Bits) DMA_LCD_TOP_ LCD top address for frame buffer 2 0xFFFEDB0A F2_L lower bits DMA_LCD_TOP_ LCD top address for frame buffer 2 0xFFFEDB0C F2_U upper bits DMA_LCD_BOT_ LCD bottom address for frame buffer 0xFFFEDB0E F2_L 2 lower bits...
Page 274: Generic Channel Registers
Registers 5.6.1 Generic Channel Registers There is one set of these registers for each generic DMA channel. Although the DMA has a 32-bit TIPB, all registers are in 16-bit format and must be accessed as 16-bit data by the MPU. Table 5–12.
Page 275: Channel Source Destination Parameters Register (Dma_Csdp)
Registers Table 5–12. Channel Source Destination Parameters Register (DMA_CSDP) (Continued) Reset Name Value Description Type Value 12–9 Transfer destination 0000 A unique identifier is given to each port. This field indicates which port is the originator of the transfer. 0000 EMIFF 0001 EMIF...
Page 276 Registers Table 5–12. Channel Source Destination Parameters Register (DMA_CSDP) (Continued) Reset Name Value Description Type Value SRC_PACK Source packing The DMA ports can have a data bus width different from that of the type of data moved by the DMA channel. For example, s8 data can be read on a 32-bit DMA port.
Page 277 Registers Table 5–12. Channel Source Destination Parameters Register (DMA_CSDP) (Continued) Reset Name Value Description Type Value 1–0 DATA_TYPE Defines the type of the data moved in the channel s8, 8 bits scalar s16, 16 bits scalar s32, 32 bits scalar Illegal value Start address must be aligned on the boundary of the type of data moved.
Page 278 Registers Table 5–13. DMA Channel Control Register (DMA__CCR) Reset Name Value Description Type Value 15–14 DST_AMODE Destination addressing mode This field is used to choose the addressing mode on the destination port of a channel. Constant address Post-incremented address Single index (element index) Double index (element index and frame index) 13–12 SRC_AMODE Source addressing mode...
Page 279: Dma Channel Control Register (Dma
Registers Table 5–13. DMA Channel Control Register (DMA__CCR) (Continued) Reset Name Value Description Type Value AUTO_INIT Autoinitialization at the end of the transfer The channel stops at the end of the current transfer. When the current transfer is complete, the channel automatically reinitializes itself and starts a new transfer.
Page 280 Registers Table 5–13. DMA Channel Control Register (DMA__CCR) (Continued) Reset Name Value Description Type Value Frame synchronization This bit is used to program the way a DMA request is serviced in a synchronized transfer. An element is transferred each time a DMA request is made.
Page 281: Dma Channel Interrupt Control Register (Dma_Cicr)
Registers Table 5–14. DMA Channel Interrupt Control Register (DMA_CICR) Reset Name Value Description Type Value 15–7 RESERVED RESERVED BLOCK_IE End block interrupt enable The channel does not interrupt the processor when the transfer of the block completes. The channel sends an interrupt to the processor when the transfer of the block completes.
Page 282: Dma Channel Status Register (Dma_Csr)
Registers Table 5–14. DMA Channel Interrupt Control Register (DMA_CICR) (Continued) Reset Name Value Description Type Value TOUT_IE Time-out interrupt enable The DMA does not send an interrupt to the processor if a time-out error occurs. The DMA sends an interrupt to the processor if a time-out error occurs either in the source or in the destination port of the channel.
Page 283 Registers Table 5–15. DMA Channel Status Register (DMA_CSR) (Continued) Reset Name Value Description Type Value SYNC Synchronization status This bit is not set to one when an interrupt is generated, but when a DMA request is made in a synchronized channel. When the DMA request is serviced, the bit returns to zero.
Page 284: Dma Channel Source Start Address-Lower Bits Register (Dma_Cssa_L)
Registers This register is written by the DMA to reflect the channel status. It can be read by the processor (by polling or after an interrupt) to see the channel status. Af- ter a functional read, all the DMA_CSR bits are automatically cleared. The DMA_CSR bit is not cleared after an emulation read via the debugger.
Page 285: Dma Channel Destination Start Address-Upper Bits Register (Dma_Cdsa_U)
Registers Table 5–19. DMA Channel Destination Start Address–Upper Bits Register (DMA_CDSA_U) Reset Name Description Type Value 15–0 Destination Upper bits for the source start address, expressed in Undefined start address, bytes. The destination start address is made of the upper bits concatenation of DMA_CDSA_U and DMA_CDSA_L.
Page 286: Dma Channel Element Index Register (Dma_Cei)
Registers Table 5–23. DMA Channel Element Index Register (DMA_CEI) Reset Name Description Type Value 15–0 Element index Contains the element index, expressed in bytes, used to Undefined compute the addresses when single-index addressing mode is used. Table 5–24. DMA Channel Progress Counter Register (DMA_CPC) Reset Name Description...
Page 287: Dma Lcd Control Register (Dma_Lcd_Ctrl)
Registers Table 5–25. DMA LCD Control Register (DMA_LCD_CTRL) Reset Name Value Description Type Value 15–7 RESERVED LCD_SOURCE Memory source for the LCD channel This bit indicates the memory source for the next LCD transfer. Memory source is EMIFF. Memory source is IMIF. BUS_ERROR_ Status LCD channel register (must be reset after R–R...
Page 288: Lcd Top Address For Frame Buffer 1-Lower Bits Register
Registers Table 5–25. DMA LCD Control Register (DMA_LCD_CTRL) (Continued) Reset Name Value Description Type Value FRAME_MODE Kind of frame mode used for LCD transfer One frame buffer; only registers for frame 1 are used. Two frame buffers; LCD channel reads alternatively top_frame_1 and top_frame_2 5.6.1.1 LCD Top Address for Frame Buffer 1 Registers (DMA_LCD_TOP_F1_L and...
Page 289: Lcd Bottom Address For Frame Buffer 1 Register-Lower Bits Register
Registers 5.6.1.2 LCD Bottom Address for Frame Buffer 1 Registers (DMA_LCD_BOT_F1_L and DMA_LCD_BOT_F1_ The LCD bottom address registers are two 16-bit registers that contain the bottom address for the video RAM buffer 1. The 32-bit address is obtained by the concatenation of the two 16-bit words as described here: LCD_BOTTOM_F1 = DMA_LCD_BOT_F1_U and DMA_LCD_BOT_F1_L Note: LSB of the 32-bit word is equal to zero.
Page 290: Lcd Top Address For Frame Buffer 2-Lower Bits Register
Registers 5.6.1.3 LCD Top Address for Frame Buffer 2 Registers (DMA_LCD_TOP_F2_L and DMA_LCD_TOP_F2_U) The LCD top address registers are two 16-bit registers that contain the start address for the video RAM buffer 2. The 32-bit address is obtained by the concatenation of the two 16-bit words as described here: LCD_TOP_F2 = DMA_LCD_TOP_F2_U &...
Page 291: Lcd Bottom Address For Frame Buffer 2-Lower Bits Register
Registers 5.6.1.4 LCD Bottom Address for Frame Buffer 2 Registers (DMA_LCD_BOT_F2_L and DMA_LCD_BOT_F2_U) The LCD bottom address registers are two 16-bit registers that contain the bottom address for the video RAM buffer 2. The 32-bit address is obtained by the concatenation of the two 16-bit words as described here: LCD_BOTTOM_F2 = DMA_LCD_BOT_F2_U and DMA_LCD_BOT_F2_L Note: LSB of the 32-bit word is equal to zero.
Page 292: Mpu Private Peripherals
Chapter 6 MPU Private Peripherals This chapter describes the OMAP5910 multimedia processor MPU private peripherals. Topic Page Overview ........... . .
Page 293: Overview
The configuration module allows the software to control the different OMAP5910 modes. The device identification registers allow the software to read the different OMAP5910 identification codes. Figure 6–1 shows the OMAP5910 device with the MPU private peripherals highlighted. Figure 6–1. MPU Private Peripherals...
Page 294: 32-Bit Timer
Timer Description 6.2 Timer Description Three 32-bit timers for the operating system provide general-purpose house- keeping functions. These timers are configured either in autoreload or one- shot mode with on-the-fly read capability. The timers generate an interrupt to the TI925T RISC processor when equal to zero. Figure 6–2 shows the 32-bit timer.
Page 295: Ptv Value And Corresponding Division Value
Timer Description Table 6–2 provides division values for each PTV field. Table 6–2. PTV Value and Corresponding Division Value Divisor The timer interrupt period is determined in the following manner, where t the clock period of the input clock, LOAD_TIM (see Table 6–1) is the register that holds the value loaded when the timer passes through 0 or when it starts, and PTV is the prescaler field located in the control timer register (CNTL_TIMER):...
Page 296: Timer Diagram
Timer Description If LOAD_TIM = 0 and AR (auto-reload mode) = 1, the timer is always 0 and can never decrement. Here the timer interrupt is asserted and stays asserted all the time. Since the timer interrupts are edge-senditive, only one interrupt is recognized because there is one initial edge, and then the interrupt is asserted constantly.
Page 297: Timer Registers
Timer Description 6.2.2 Timer Registers Table 6–4 lists the timer registers. Table 6–5 through Table 6–7 describe the register bits. Base address for timer 1: FFFE:C500 Base address for timer 2: FFFE:C600 Base address for timer 3: FFFE:C700 Bit width: 32 bits Table 6–4.
Page 298 Timer Description Table 6–6. Load Timer Register (LOAD_TIMER) Reset Name Description Value 31–0 LOAD_TIM The value is loaded into the VALUE_TIM when the timer passes Undefined through 0 or when it starts. Table 6–7. Read Timer Register (READ_TIMER) Reset Name Description Value 31–0...
Page 299: Watchdog Timer Level 1 Interrupt
Watchdog Timer 6.3 Watchdog Timer The watchdog timer (see Figure 6–4) can be configured as either a watchdog timer or a general-purpose timer. 6.3.1 Introduction The watchdog timer is power-up enabled and defaults to watchdog timer for the TI925T RISC processor. A watchdog timer requires that the user program or OS periodically write to the count register before the counter underflows.
Page 300: Ptv Value And Associated Divisor Value
Watchdog Timer By default, this timer is configured as a watchdog timer and generates a reset of the TI925T RISC processor approximately every 19 seconds, unless you disable or update properly. If you do not, you may during system development encounter an unexpected reset every 19 seconds or so.
Page 301: Watchdog Timer Characteristics
Watchdog Timer (PTV+1) X (LOAD_TIM + 1) x 2 Table 6–10 shows the characteristics of the watchdog timer for different LOAD_TIM values. Table 6–10. Watchdog Timer Characteristics Input clock, , Timer Interrupt Period, † LOAD_TIM CLKIN Clock Period for PTV = 7 597.34 µs 12 MHz 1167 ns...
Page 302: Timer Diagram
Watchdog Timer When the timer has been configured as a general-purpose timer, it can be switched back to watchdog mode by writing a 1 to the watchdog bit of the TIMER_MODE register. In this case, the value loaded into LOAD_TIM is set to the maximum value (0xFFFF) as on power up.
Page 303: Watchdog Timer
Watchdog Timer 6.3.4 Watchdog Timer Registers Table 6–11 lists the watchdog timer registers. Table 6–12 through Table 6–15 describe the register bits. Base address for watchdog timer: FFFE:C800 Bit width: 32 bits Table 6–11. Watchdog Timer Registers Reset Name Description Size Offset Value...
Page 304: Load Timer Register (Load_Tim)
Watchdog Timer Table 6–13. Load Timer Register (LOAD_TIM) Reset Name Description Value 15–0 LOAD_TIM General-purpose timer: FFFF This value is loaded when timer passes through 0 or when it starts. Watchdog timer: Reload timer with this value. Table 6–14. Read Timer Register (READ_TIM) Reset Name Description...
Page 305: Mpu Interrupt Handlers
MPU interrupt (IRQ or FIQ—see Figure 6–6) inputs according to that interrupt ILRn configuration bit. A clock request mechanism is implemented to wake up and provide a clock to the interrupt handler when the OMAP5910 device is in one of the sleep modes. 6-14...
Page 306: Mpu Interrupt Handlers
MPU Interrupt Handlers Figure 6–6. MPU Interrupt Handlers Level 2 Level 1 interrupt Interrupt handler Handler IRQ from Level2 FIQ from Level 1 IRQ 0 IRQ 0 Keypad Camera interrupt IRQ from Level 1 IRQ 1 IRQ 1 MicroWire transmit Reserved IRQ 2 IRQ 2...
Page 307: Mpu Level 2 Interrupt Handler
6.4.2 MPU Level 2 Interrupt Handler Because the number of interrupts that the OMAP5910 device must manage is greater than 32, a second interrupt handler is used. The resulting interrupt is connected to the IRQ_0 of the TI925T RISC processor interrupt handler, which must be programmed as a level interrupt.
Page 308: Level 1 And Level 2 Omap5910 Mpu Interrupt Mapping
IRQ_ABORT (IRQ_9) is the traffic controller abort IRQ. It is also connected to DSP IRQ_12. This interrupt comes from either a TIPB bus or the MPUI and is caused by a time-out abort. Table 6–16. Level 1 and Level 2 OMAP5910 MPU Interrupt Mapping Default Sensitivity...
Page 309 Level 1 and Level 2 Interrupt Mapping Table 6–16. Level 1 and Level 2 OMAP5910 MPU Interrupt Mapping (Continued) Default Sensitivity Interrupt Line Interrupt Line Incoming Interrupts Configuration on Level 1 on Level 2 IRQ_DMA_CH3 Level IRQ_22 — IRQ_DMA_CH4 Level IRQ_23 —...
Page 310 Level 1 and Level 2 Interrupt Mapping Table 6–16. Level 1 and Level 2 OMAP5910 MPU Interrupt Mapping (Continued) Default Sensitivity Interrupt Line Interrupt Line Incoming Interrupts Configuration on Level 1 on Level 2 MCSI1 combined TX/RX/frame error Level IRQ0...
Page 311: Interrupt Handler Level 1 And Level 2 Registers
Interrupt Handler Level 1 and Level 2 Registers 6.6 Interrupt Handler Level 1 and Level 2 Registers There are two sets of interrupt handler registers: one for the level 1 handler, the other for the level 2 handler (see Table 6–17). Table 6–18 through Table 6–24 describe the register bits.
Page 312: Interrupt Handler Registers
Interrupt Handler Level 1 and Level 2 Registers Table 6–17. Interrupt Handler Registers (Continued) Reset Name Description Bits Offset Value ILR15 Interrupt priority level for IRQ 15 7 bits 0X58 0x00 ILR16 Interrupt priority level for IRQ 16 7 bits 0X5C 0x00 ILR17...
Page 313: Mask Interrupt Register (Mir)
Interrupt Handler Level 1 and Level 2 Registers Table 6–18. Interrupt Input Register(ITR) Reset Name Description Value IRQ_31 Interrupt request—1 indicates that the peripheral occupying the IRQ_31 address space has requested interrupt service from the MPU. An edge-triggered interrupt is stored in this register as an incoming interrupt.
Page 314: Interrupt Level Registers (Ilr0
Interrupt Handler Level 1 and Level 2 Registers Table 6–21. Binary-Coded Source FIQ Register (SIR_FIQ_CODE) Reset Name Description Value 4–0 FIQ_NUM This register indicates the IRQ interrupt that is currently being serviced by the MPU. Reading this register clears the corresponding bit in the ITR register if the interrupt is configured as edge triggered.
Page 315: Configuration Module
The OMAP5910 configuration module allows the software of the OMAP5910 device to control the various static modes supported by the device. This module is the primary point of control for the following areas of the OMAP5910 device: Functional I/O multiplexing...
Page 316: Omap5910 Generic Pin Multiplexing And Pullup/Pulldown Control
0x0000EAEFh to the COMP_MODE_CTRL_0 register to utilize the pin multiplexing and device configuration features available in native mode. Be careful when enabling the native mode. All OMAP5910 configuration registers reset to 0x0000h at power-on reset. It is advisable to follow the following procedure before enabling the OMAP5910 mode: 1) Determine the desired values for each OMAP5910 configuration register.
Page 317: Omap5910 Mmc/Sd Pin Multiplexing
The OMAP5910 device implements both pullups and pulldowns on several I/Os. In this document there are several references to pulldowns and pulldown enables. It is proper to assume that if an OMAP5910 device pin has a pullup, the corresponding pulldown enables (enables = 0/disables = 1) the pullup.
Page 318: (Func_Mux_Ctrl3
OMAP5910 Configuration Registers 6.8 OMAP5910 Configuration Registers Table 6–26 lists the 32-bit read/write configuration registers. Table 6–27 through Table 6–49 describe the register bits. The compatibility mode control 0 register (COMP_MODE_CTRL_0) must be programmed to 0xEAEFh for any of these configuration registers to exercise their associated control. The base address for the configuration registers is FFFE:1000.
Page 319: Functional Multiplexing Control 0 Register (Func_Mux_Ctrl_0)
Reserved. These bits must always be written as LB_RESET_DISABLE This bit holds the OMAP local bus reset input active. Set this to 1 when using OMAP5910 USB_HHC module. Local bus RESET <= 0 Local bus RESET <= USB_HHC LB reset This bit is valid in compatibility and native modes.
Page 320 USB input vbus_ctrl <= OMAP5910 configuration VBUS_CTRL bit 17–15 RESERVED Reserved. These bits must always be written as NRESET_ENABLE Allows AND gating of OMAP5910 outputs with the OMAP CHIP_NRESET_OUT Disabled Allowed This bit is valid in compatibility and native modes.
Page 321: Functional Multiplexing Control 1 Register (Func_Mux_Ctrl_1)
Reset Name Value Description Value PWR_MASK_OUT Does not allow AND gating of OMAP5910 outputs with COM_PWR_REQ (GPIO9) and COM_STS (MPUIO3) OMAP5910 input pins Allows AND gating of OMAP5910 outputs with COM_PWR_REQ (GPIO9) and COM_STS (MPUIO3) OMAP5910 input pins This bit is valid in compatibility and native modes.
Page 322: Functional Multiplexing Control 2 Register (Func_Mux_Ctrl_2)
Reserved. These bits must always be written as 0. 0x00000000 At reset, the OMAP5910 device configuration registers are software compat- ible with previous prototype devices. Writing an 0x0000EAEFh to the compati- bility mode control 0 register (COMP_MODE_CTRL_0) enables the new functional multiplexing registers found at offset 0x10h and above.
Page 323: Compatibility Mode Control 0 Register (Comp_Mode_Ctrl_0)
Name Description Value 31–16 RESERVED Reserved for future expansion. These bits must be 0x0000 written to 0x0000h when enabling the OMAP5910 configuration registers. 15–0 CONF_COMPATIBILITY_R These bits must be written to 0x0000EAEFh to 0x0000 enable OMAP5910 configuration bits at offset 0x10h and above.
Page 324: Functional Multiplexing Control 5 Register (Func_Mux_Ctrl_5)
Name Description Value 23–21 CONF_CAM_EXCLK_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to CAM.EXCLK at reset. The control for this I/O is forced to 000 at reset and while in compatibility mode. 20–18 RESERVED Reserved for future expansion. These bits must always be written as 0.
Page 325 Name Description Value 26–24 CONF_CAM_HS_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to CAM.HS at reset. The control for this I/O is forced to 000 at reset and in compatibility mode. 23–21 CONF_CAM_VS_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to CAM.VS at...
Page 326: Functional Multiplexing Control 6 Register (Func_Mux_Ctrl_6)
Reserved for future expansion. These bits must always be written as 0. 29–27 CONF_GPIO_4_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to GPIO4 at reset. The control for this I/O is forced to 000 at reset and while in compatibility mode.
Page 327 Bits Name Description Value 17–15 CONF_GPIO_12_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to GPIO12 at reset. The control for this I/O is forced to 000 at reset and while in compatibility mode. 14–12 CONF_GPIO_13_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to GPIO13 at reset.
Page 328: Functional Multiplexing Control 7 Register (Func_Mux_Ctrl_7)
Reserved for future expansion. These bits must always be written as 0. 20–18 CONF_ARMIO_2_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to MPUIO2 at reset The control for this I/O is forced to 000 at reset and while in compatibility mode.
Page 329: Functional Multiplexing Control 8 Register (Func_Mux_Ctrl_8)
Reserved for future expansion. These bits must always be written as 0. 29–27 CONF_ARM_BOOT_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to MPU_BOOT at reset. The control for this I/O is forced to 000 at reset and while in compatibility mode. 26–15 RESERVED Reserved for future expansion.
Page 330: Functional Multiplexing Control 9 Register (Func_Mux_Ctrl_9)
The control for this I/O is forced to 000 at reset and in compatibility mode. 23–21 CONF_TX1_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to UART1.TX at reset. The control for this I/O is forced to 000 at reset and in compatibility mode. 20–15 RESERVED Reserved for future expansion.
Page 331: Functional Multiplexing Control A Register (Func_Mux_Ctrl_A)
0. 26–24 CONF_MMC_DAT1_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to MMC.DAT1 at reset. As long as the STATIC_VALID pin is sampled high upon reset, the control for this I/O is force to 000 at reset and while in compatibility mode.
Page 332: Functional Multiplexing Control B Register (Func_Mux_Ctrl_B)
2–0 CONF_UARTS_CLKIO_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to BCLK at reset. The control for this I/O is forced to 000 at reset and in compatibility mode. Table 6–39. Functional Multiplexing Control B Register (FUNC_MUX_CTRL_B)
Page 333: Functional Multiplexing Control C Register (Func_Mux_Ctrl_C)
Name Description Value 8–6 CONF_MCSI2_DIN_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to MCSI2.DIN at reset. The control for this I/O is forced to 000 at reset and in compatibility mode. 5–3 CONF_MCSI2_CLK_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to MCSI2.CLK at...
Page 334 Name Description Value 20–18 CONF_RX2_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to UART2.RX at reset. The control for this I/O is forced to 000 at reset and while in compatibility mode. 17–15 CONF_MCBSP2_DOUT_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to MCBSP2.DOUT...
Page 335: Functional Multiplexing Control D Register (Func_Mux_Ctrl_D)
0x00000 always be written as 0. 14–12 CONF_MMC_DAT3_R These bits control the multiplexing on the OMAP5910 I/O, which defaults to MMC.DAT3 at reset The control for this I/O is forced to 000 at reset. 11–9 RESERVED Reserved for future expansion. These bits must always be written as 0.
Page 336: Pulldown Control 0 Register (Pull_Dwn_Ctrl_0)
Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 337: Pulldown Control 1 Register (Pull_Dwn_Ctrl_1)
Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 338 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 339 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 340 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 341 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 342 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 343 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 344: Pulldown Control 2 Register (Pull_Dwn_Ctrl_2)
Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 345 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 346 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 347 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 348 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 349 Depending upon the pin multiplexing config- uration of any particular I/O, a pulldown may not be available. Consult Appendix A of this document or the OMAP5910 data manual (literature number SPRS197) to determine whether a pulldown exists for each I/O.
Page 350: Pulldown Control 3 Register (Pull_Dwn_Ctrl_3)
Reserved for future expansion. These 0x00000 bits must always be written as 0. CONF_PDEN_NTRST_R This bit controls the pulldown enable on the OMAP5910 I/O, which defaults to TRST at reset. Pulldown enabled Pulldown disabled CONF_PDEN_TCK_R This bit controls the pulldown enable on the OMAP5910 I/O, which defaults to TCK at reset.
Page 351: Gate And Inhibit Control 0 Register (Gate_Inh_Ctrl_0)
Reset Name Value Description Value CONF_PDEN_MMC_DAT3_R This bit controls the pullup enable on the OMAP5910 I/O, which defaults to MMC.DAT3 at reset. Pulldown enabled Pulldown disabled 7–2 RESERVED Reserved for future expansion. These bits must always be written as 0.
Page 352 Value Description Value CONF_ This bit controls software gating and SOFTWARE_PWR_R inhibiting of the OMAP5910 I/O, which are gated or inhibited by COM_PWR status. If the gating and inhibiting logic are enabled by FUNC_MUX_CTRL_0 (10 – 13) bits and conf_software_gate_ena_r is set to 1, this bit controls the com_pwr gating and inhibiting instead of device pins.
Page 353: Voltage Control 0 Register (Voltage_Ctrl_0)
These bits must always be written as 0. CONF_VOLTAGE_COMIF_R This bit controls the drive strength of the OMAP5910 communication processor interface I/O. This allows the interface to be run at 1.8 V nom or 2.75 V nom. Drive strength is 1.80 V Drive strength is 2.75 V...
Page 354: Test Debug Control 0 Register (Test_Dbg_Ctrl_0)
Description Value CONF_VOLTAGE_FLASH_R This bit controls the drive strength of the OMAP5910 flash interface I/O. This allows the interface to be run at 1.8 V nom or 2.75 V nom. Drive strength is 1.80 V Drive strength is 2.75 V At reset and in compatibility mode, the interface is set for 2.75-V...
Page 355: Module Configuration Control 0 Register (Mod_Conf_Ctrl_0)
Name Value Description Value CONF_MOD_UART3_ This bit determines the clock source of CLK_MODE_R UART3 on the OMAP5910 device. 12 MHz 48 MHz CONF_MOD_UART2_ This bit determines the clock source of CLK_MODE_R UART2 on the OMAP5910 device. 32 kHz/12 MHz (see Chapter 12, UART...
Page 356 Description Value CONF_MOD_MMC_SD_ This is the functional 48-MHz clock request CLK_REQ_R for the OMAP5910 device MMC/SD interface. This bit resets to 0 at reset. This corresponds to the MMC/SD clock not being requested. Set the bit to 1 to request the clock for the MMC/SD interface.
Page 357 This bit allows the user to force the EMRS_BA1_CTRL SDRAM SDRAM.BA[1] pin to a high. With proper disabling of SDRAM accesses from OMAP5910, users can use this to program the EMRS register of the SDRAM with an MRS write instruction. There are no hardware hooks to only assert this when performing an MRS write.
Page 358 Value CONF_MOD_COM_ This bit determines if the UART2.CLKREQ MCLK_12_48_SEL_R output of the OMAP5910 device is 12 MHz or 48 MHz. This bit resets to 0, which causes a 12-MHz clock to be seen on MCLK when UART2.CLKREQ is low. When written to a 1, this bit causes 48-MHz clock to be seen on MCLK when UART2.CLKREQ is low.
Page 359 OMAP5910 Configuration Registers Table 6–49. Module Configuration Control 0 Register (MOD_CONF_CTRL_0) (Continued) Reset Name Value Description Value CONF_MOD_USB_HOST_ Transceiverless link logic (TLL) USB speed HMC_TLL_SPEED_R control. For HMC modes (as defined by HMC_MODE_I and HMC_JTAG_EN_I) where the TLL is used, determines whether the modelling of the device pullup resistor is on the internal D+ or internal D–...
Page 360 OMAP5910 Configuration Registers Table 6–49. Module Configuration Control 0 Register (MOD_CONF_CTRL_0) (Continued) Reset Name Value Description Value CONF_MOD_USB_HOST_ Transceiverless link logic (TLL) USB attach HMC_TLL_ATTACH_R control. For HMC modes (as defined by HMC_MODE_I and HMC_JTAG_EN_I) where the TLL is used, determines whether...
Page 361: Id Code Register (Idcode)
Device Identification 6.9 Device Identification The device identification can be done by software via two registers: The identification code (IDCODE) register identifies the OMAP5910 device. The identification die (ID) register identifies the die. 6.9.1 Identification Code Register The identification code register (IDCODE), shown in Table 6–50, can be split...
Page 362: Die Id Address Space-Private Tipb Bridge
The die ID can be read by software via the private TIPB (see Table 6–52). Table 6–52. Die ID Address Space—Private TIPB Bridge Data Device Name Start Address Size in Bytes Access OMAP5910 Die ID FFFE:1800 4 bytes OMAP5910 Die ID FFFE:1804 4 bytes MPU Private Peripherals...
Page 363: Mpu Public Peripherals
Chapter 7 MPU Public Peripherals This chapter describes the MPU public peripherals. Topic Page MPU Public Peripherals ........Camera Interface .
Page 364: Mpu Public Peripherals Area
MPU Public Peripherals 7.1 MPU Public Peripherals Figure 7-1 shows the OMAP5910 device with the MPU public peripherals highlighted. Figure 7-1. MPU Public Peripherals Area DSP private Private peripherals OMAP5910 peripheral bus Timers (3) DSP public peripherals Watchdog timer TMS320C55x DSP...
Page 365: Camera Interface
7.2 Camera Interface An 8-bit camera interface (32-bit internal bus on the TIPB side) connects a camera module to the MPU peripheral bus of the OMAP5910 device. The in- terface handles multiple image formats synchronized on vertical and horizon- tal synchronization signals. Data transfer between camera and interface can be done synchronously or asynchronously.
Page 366: Camera Interface Block Diagram
Camera Interface Figure 7-2. Camera Interface Block Diagram Camera I/F CAM_D TIPB CAM_LCLK FIFO DMA_REQ CAM_VS CAM_HS TIPB register CAM_NIRQ Interrupt generator Interrupt status DPLL_REQ Clock CAM_EXCLK divider DPLL_CLK ENABLE 12 MHz...
Page 367: Image Data Transfer
Camera Interface Figure 7-3. Image Data Transfer CAM_LCLK CAM_VS CAM_HS CAM_D TIPB FIFO DMA_REQ Select order 7.2.1.1 Camera Data Validation The incoming byte on CAM_D can be latched on the rising or falling edge of CAM.LCLK generated by the camera itself. The POLCLK bit can select the polarity of CAM.LCLK in the clock control register.
Page 368: Timing Chart Of Image Data Transfer (Polclk = 1)
Camera Interface If either CAM_VS or CAM_HS goes inactive before receiving all four bytes, the data in buffers is cleared by the active CAM.LCLK edge and is not written into FIFO. Figure 7-4. Timing Chart of Image Data Transfer (POLCLK = 1) CAM_VS CAM_HS CAM_LCLK...
Page 369: Order Of Camera Data On Tipb (Not Swapped)
Camera Interface You should use the RAZ_FIFO bit to clear any remaining data in FIFO before starting a new transfer. This bit also resets all status and control signals related to the FIFO, and it disables interrupt generation from the camera interface, so the RAZ_FIFO bit must be inactive before any camera interface transfers are started.
Page 370 Camera Interface 7.2.1.5 FIFO Buffer (128 x 32) A write access is applied to the FIFO for each 32-bit word received. When the write FIFO counter reaches the trigger level, an interrupt request can be generated. The trigger level is programmable. In DMA mode, you can program the threshold between 1 and 128, but the DMA must be set up to read the threshold amount out of FIFO per the DMA request issued by the camera interface.
Page 371: Fifo Buffer Parts
Camera Interface Figure 7-8. FIFO Buffer Parts CAMERA Buffering Word y Buffering Word Q Buffering Word I DMA_REQ Block Word 1 TIPB When the threshold value is set to 0, the interrupt is generated immediately. This is the equivalent of the threshold always being exceeded regardless of whether any data is present in the FIFO.
Page 372: Irq Generated On Vsync Falling Edge
2) High level of HSYNC and proper clock edge start the first data transfer from the camera to the OMAP5910 camera interface. After the first two pixels of data are received (8 bits x 4 transfers = 32 bits), a DMA request is made.
Page 373: Default Configuration At Reset
Camera Interface 3) The camera, the OMAP5910 device camera interface, and the system DMA continue transfer of data. That is, 352/2 * 288 = 50688 transfers for a camera interface image format. After the full image is transferred, the DMA sends an interrupt to the TI925T to signal that the end of frame occurred.
Page 374: Camera Interface Registers
Camera Interface 7.2.1.10 Camera Interface Registers (FFFB:6800) Because the TIPB register read accesses are resynchronized to the camera interface clock, the MCLK_EN bit must first be set before any camera interface register reads are performed. Table 7-3 lists the camera interface registers. Table 7-4 through Table 7-10 describe the individual registers.
Page 375: Interrupt Source Status Register (It_Status)
Camera Interface Table 7-4. Clock Control Register (CTRLCLOCK) (Continued) Reset Name Value Function Value CAMEXCLK_EN Disables Enables CAM.EXCLK POLCLK Sets polarity of CAM.LCLK Data latched on rising edge Data latched on falling edge FOSCMOD Sets the frequency of the CAM.EXCLK clock 0x00 12 MHz 6 MHz...
Page 376: Camera Interface Mode Configuration Register (Mode)
Camera Interface Table 7-6. Camera Interface Mode Configuration Register (MODE) Reset Name Value Function Value 31-19 RESERVED Reserved bits RAZ_FIFO When 1: Clears data in the FIFO; reinitializes read and write pointers; clears FIFO full interrupt, FIFO peak counter; and resynchronizes. EN_FIFO_FULL Disables Enables interrupt on FIFO_FULL...
Page 377: Camera Interface Gpio Register (Gpio)
Camera Interface Table 7-6. Camera Interface Mode Configuration Register (MODE) (Continued) Reset Name Value Function Value IMGSIZE Sets image size 0x00 QCIF QVGA Currently, these bits have no effect on the operation of the camera interface. CAMOSC Set synchronous mode Set asynchronous mode Currently this has no effect on the camera interface.
Page 378: Image Data Register (Camdata)
Camera Interface Table 7-9. Image Data Register (CAMDATA) Reset Name Function Value 31-0 CAMDATA Image data from FIFO Table 7-10. FIFO Peak Counter Register (PEAK_COUNTER) Reset Name Function Value 31-7 RESERVED Reserved Unknown PEAK_COUNTER Maximum number of words written to FIFO 0x0000000 during the transfer since the last clear to zero 7.2.2...
Page 379: Mpu I/O Interrupts
The MPU I/O module has two clocks: The 32-kHz system clock (CLK_32KHZ), which comes, through the ULPD, from either the OMAP5910 32-kHz oscillator or the OMAP5910 CLK32K_IN CMOS input. For more detail, see Chapter 15, Clock Generation and System Reset Management).
Page 380 Clock Generation & Management NOTES: kbc(6) (1): These brackets mean that these WIRE_nSCS3 (KBC(6) MPU IOs are not present by default on OMAP5910 pads (2): These Pull-downs have dotted line because they don’t exist for all these kbc(5:0) KBC(5:0) MPU IOs...
Page 381: Keyboard Scanning Sequence
MPU I/O 7.3.3 MPUIO Keyboard Interface To allow button press detection: All the row lines (KB.R) must have an external pullup. All the column lines (KB.C) drive a low level (idle state of Table 7-11). The output drivers of the KBC output pins act as open-drain outputs in that they only drive low or are 3-state.
Page 382: Keyboard Process Block Diagram
Edge detection can be used to latch all the GPIOs (event capture mode). GPIO interface works with the 32-kHz-system clock and consequently can be used to wake up the OMAP5910 device by generating the GPIO interrupt. 7-20...
Page 383: Gpio Process
MPU I/O Figure 7-12. GPIO Process Interrupt edge Interrupt mask GPIO_INT_EDGE_REG GPIO_MASKIT GPIO_DEBOUNCING_REG and GPIO MASKIT If yes, then GPIO Transition matches MPUIO_IN(15:0) Debouncing interrupt GPIOS_INT the programmed time (steps of edge and not 31 µs) masked? 31 µ-8 ms CPU read: GPIO_INT status INPUT_LATCH...
Page 384: Gpio_Int Register Read Timing
MPU I/O Figure 7–13. GPIO_INT Register Read Timing CLK_32KHz MPUIO_IN(I) GPIOS_INT NSTROBE TIPB access cycle GPIO_INT Reg reset The GPIO_INT read asynchronously resets the gpios_int interrupt. GPIO_INT read occurs during GPIO_INT read occurs during the the clk_32 kHz low level. The clk_32 kHz high level.
Page 385: Mpu I/O Input Masking Timing
MPU I/O debouncing period; the debouncing is then forced dynamically to 0 and the interrupt is generated five cycles after the mask presence. You must decide whether or not to mask these interrupts by maintaining or releasing the mask activation. When one detected edge is masked, the event is not reset when a GPIO_INT register read occurs.
Page 386: Event Capture Module
MPU I/O 7.3.7 Event Capture Module The GPIO event capture mode allows latching the input value present on the GPIO ports each time a rising or a falling edge occurs on a selected GPIO port, here called GPIO_CLK. If not masked, the GPIO_CLK-selected edge generates an interrupt to the processor, as shown in Figure 7–15.
Page 387: Event Capture Process
MPU I/O Figure 7–16. Event Capture Process Interrupt edge Interrupt mask GPIO_INT_EDGE_REG GPIO_MASKIT GPIO_DEBOUNCING_REG and GPIO MASKIT If yes, then GPIO Transition matches MPUIO_IN(15:0) Debouncing Interrupt the programmed time (steps of edge and not 31 µs) masked? 31 µ-8 ms GPIO_INT status Clock event and pin select register:...
Page 388: General-Purpose Input Register (Input_Latch)
MPU I/O Table 7–12. MPU Input/Output Registers (Continued) Register Description Size Address Offset GPIO_INT GPIO interrupt 16 bits FFFB:5000 0x24 KBD_MASKIT Keyboard mask interrupt 16 bits FFFB:5000 0x28 GPIO_MASKIT GPIO mask interrupt 16 bits FFFB:5000 0x2C GPIO_DEBOUNCING_REG GPIO debouncing 16 bits FFFB:5000 0x30 GPIO_LATCH_REG...
Page 389: Keyboard Row Inputs Register (Kbr_Latch)
MPU I/O Table 7–16. Keyboard Row Inputs Register (KBR_LATCH) Reset Name Function Value 15–7 Reserved 4–0 KBR_LATCH Keyboard row inputs Reflects input pins Table 7–17. Keyboard Column Outputs Register (KBC_REG) Reset Name Function Value 15–8 Reserved 7–0 KBC_REG Keyboard columns outputs Table 7–18.
Page 390: Keyboard Interrupt Register (Kbd _Int)
MPU I/O Table 7–20. Keyboard Interrupt Register (KBD _INT) Reset Name Function Value 15–1 Reserved KBD_INT Keyboard interrupt (active low) Note: KBD_INT is a status bit only (duplication of the level of the corresponding interrupt signal). Table 7–21. GPIO Interrupt Register (GPIO_INT) Reset Name Function...
Page 391: Gpio Debouncing Register (Gpio_Debouncing_Reg)
MPU I/O Table 7–24. GPIO Debouncing Register (GPIO_DEBOUNCING_REG) Reset Name Function Value 15–9 Reserved 000000000: 0 µσ to 31 µs debouncing time 8–0 GPIO_ 0000 DEBOUNCING_REG 100000010: 7,97 ms to 8 ms debouncing time Programming step is 31 µs. Note: Because GPIO_CLK is an asynchronous signal, loading GPIO_DEBOUNCING_REG with 01 hex minimum value is rec- ommended to ensure that you have a 31-µs minimum debouncing time.
Page 392: Block Diagram
MicroWire Interface 7.4 MicroWire Interface This serial synchronous interface can drive two serial external components. For the external devices, this interface is compatible with the µWire standard and is seen as the master (see Figure 7–17). A transmit DMA mode is available. Figure 7–17.
Page 393: Transmit Data Register (Tdr)
MicroWire Interface Table 7–26. MicroWire Registers (Continued) Register Description Size Address Offset Setup 3 16 bits FFFB:3000 0x10 Setup 4 16 bits FFFB:3000 0x14 Setup 5 16 bits FFFB:3000 0x18 Table 7–27. Transmit Data Register (TDR) Reset Name Function Value 15–0 Data to transmit Undefined...
Page 394: Control And Status Register (Csr)
MicroWire Interface Table 7–29. Control and Status Register (CSR) Reset Name Value Function Value RDRB RDRB bit at 1 indicates that the receive (RDR) is full. When the controller reads the content of the RDR, this bit is cleared. This bit is read only. CSRB CSRB bit at 0 indicates that the control and status (CSR) is ready to receive new data.
Page 395: Setup Register 1 (Sr1)
MicroWire Interface Table 7–29. Control and Status Register (CSR) (Continued) Reset Name Value Function Value 11–10 INDEX Index of the external device Undefined Reserved Reserved 9–5 NB_BITS_WR Number of bits to transmit Undefined 4–0 NB_BITS_RD Number of bits to receive Undefined This register sets up the serial interface for the first and the second external components.
Page 396 MicroWire Interface Table 7–30. Setup Register 1 (SR1) (Continued) Reset Name Value Function Value 4–3 CS0_FRQ Defines the frequency of the serial clock SCLK when Undefined CS0 is selected (F_INT is the frequency of the internal clock to the microwire control logic as defined in register SR3).
Page 397: Setup Register 2 (Sr2)
MicroWire Interface This register sets up the serial interface for the first and the second external components. Table 7–31. Setup Register 2 (SR2) Reset Name Value Function Value CS3_CHK Same as CS0_CHK. Undefined Used when CS3 is selected. 10–9 CS3_FRQ Defines the frequency of the serial clock Undefined SCLK when CS3 is selected...
Page 398: Setup Register 3 (Sr3)
MicroWire Interface This register sets up the serial interface for the internal clock. Table 7–32. Setup Register 3 (SR3) Reset Name Value Function Value 2–1 CK_FREQ Defines the frequency of the internal clock, F_INT, when CLK_EN = 1. All the internal logic is controlled by F_INT (F is the frequency of the external input clock).
Page 399: Setup Register 5 (Sr5) (Read/Write)
MicroWire Interface Table 7–34. Setup Register 5 (SR5) (Read/Write) Reset Name Value Function Value CS_TOGGLE_TX_EN CS_TOGGLE_TX_EN is possible only in autotransmit mode. When in autotransmit mode with CS_TOGGLE_TX_EN inactive, the CS does not go to its active level automatically. Control the CS with the CS CMD bit of the control and status register (CSR) in the software.
Page 400: Protocol Description
MicroWire Interface Set up the DMA, IT, AUTO_TX, and CS_TOGGLE modes in this register. In DMA mode, a DMA request is initiated each time a transmission slot is available. The maximum word size in DMA mode is 16 bits. Notes: You cannot use another CS in normal or DMA mode when a DMA mode is active on one specific CS.
Page 401: Behavior Of A X25C02 Eeprom Read Cycle
MicroWire Interface Figure 7–18. Behavior of a X25C02 EEPROM Read Cycle WIRE_NCS UWIRE.SCLK A6 A5 A4 A3 A2 A1 A0 UWIRE.SDO UWIRE.SDI D6 D5 D4 D1 D0 On the DO line, data is generated from the µWire interface on SLCK falling edge and read by the EEPROM interface on SCLK rising edge.
Page 402 MicroWire Interface 7.4.3.1 Read Cycle 1) Set the following fields of the control and status register (CSR): NB_BITS_RD: 0 NB_BITS_WR: 0 INDEX: 00 CS_CMD: 1 START: 0 2) Load the transmit data register (TDR) with: 1 1 0 A7 A6 A5 A4 A3 A2 A1 A0 x x x x x x: Don’t care A7 ...
Page 403 MicroWire Interface 7.4.3.2 Write Cycle 1) Set the following fields of the control and status register (CSR): NB_BITS_RD: 0 NB_BITS_WR: 0 INDEX: 00 CS_CMD: 1 START: 0 2) Load the transmit data register (TDR) with: 1 0 1 A7 A6 A5 A4 A3 A2 A1 A0 x x x x x x: Don’t care A7 ...
Page 404: Example Of Protocol Using An Lcd Controller (Cop472-3)
MicroWire Interface 7.4.4 Example of Protocol Using an LCD Controller (COP472-3) Set up the interface by writing in setup 1 register (SR1) the following value: CS_EDGE_RD = 1 CS_EDGE_WR = 0 CSCS_LVL = 0 CS_FRQ = 10 CS_CHK = 0 In this example, a loading sequence to drive a four-digit display is described.
Page 405: Example Of Protocol Using Autotransmit Mode
MicroWire Interface 8) Wait for the CSRB bit of the control and status register (CSR) to be reset. 9) Load the transmit data register (TDR) with: D7...D0 x x x x x x x x x: Don’t care D7...D0: Data for special segment and control function 10) Set the following fields of the control and status register (CSR): NB_BITS_RD: 0 NB_BITS_WR: 8 (decimal)
Page 406: Read Cycle In Autotransmit Mode
MicroWire Interface 3) SR3 = CLK_EN: 1 CK_FREQ: 00 (must wait for 1 external clock + 1 F_INT cycle before any other register access) 4) SR4 = CLK_IN: 1 5) Set the following fields of the control and status register (CSR): NB_BITS_RD: 5 NB_BITS_WR: 7 INDEX: 00...
Page 407: Example Of Autotransmit Mode With Dma Support
MicroWire Interface 7.4.6 Example of Autotransmit Mode With DMA Support The autotransmit mode and DMA mode are controlled by the setup 5 register (SR5). The following example configures µWire for a 16-bit write access on CS1 with serial clock out not inverted, CS auto toggle enabled, DMA request enabled, and interrupt disabled: 1) Set up and enable the DMA channel.
Page 408: Khz Timer
32-kHz Timer 7.5 32-kHz Timer The MPU subsystem operating system (OS) requires interrupts at regular time intervals for OS scheduling purpose. OS time intervals can be from 1 ms to 30 ms. These time intervals can be generated using the three 32-bit OS/gener- al-purpose TI925T timers, which use CLKIN or DPLL1;...
Page 409: Timer Interrupt Period
32-kHz Timer 7.5.1.1 Overriding Normal Counting Normal operation can be overridden by using two bits in the timer control register (TCR): The timer reload bit (TRB) causes the counter to be reloaded on the next clk32-kHz cycle (whether or not the timer is counting). The timer start stop bit (TSS) causes the counter to be stopped on the next clk32-kHz cycle.
Page 410: 32-Khz Timer Registers
32-kHz Timer 7.5.2 32-kHz Timer Registers Base address for 32-kHz timer: FFFB:9000 Table 7–36 lists the 32-kHz timer registers. Table 7–38 through Table 7–40 describe the individual registers. Table 7–36. 32-kHz Timer Registers Name Description Size Address Offset Timer control 32 bits FFFB:9000 0x08...
Page 411: Timer Control Register (Cr)
32-kHz Timer Table 7–38. Timer Control Register (CR) Reset Name Value Function Value 31–4 Reserved Autoreload/start One-shot mode. When the counter reaches zero, an interrupt is generated and the timer is stopped. Sets the timer to autorestart mode IT_ENA Interrupt enable Interrupt disabled Interrupt enabled Timer reload bit...
Page 412: Pwl Block Diagram
Pseudonoise Pulse-Width Light Modulator 7.6 Pseudonoise Pulse-Width Light Modulator This pulse-width light (PWL) module provides control of LCD backlighting and keypad by employing a 4096-bit random sequence generator. This voltage- level control technique decreases the spectral power at the modulator harmonic frequencies.
Page 413: Pwl Registers
Pseudonoise Pulse-Width Light Modulator 7.6.2 PWL Registers The PWL is connected to the host with a TIPB. The PWL control is done with two 8-bit registers. All TIPB accesses are done asynchronously with the 32-kHz clock, meaning there is no TIPB wait-state insertion. Table 7–41 lists the PWL registers.
Page 414: Pulse-Width Tone
Pulse-Width Tone 7.7 Pulse-Width Tone This pulse-width tone (PWT) module generates a modulated frequency signal for the external buzzer. The frequency is programmable between 322 Hz and 4868 Hz with 12 half-tone frequencies per octave. The volume level is also pro- grammable.
Page 415: Pwt Block Diagram
Pulse-Width Tone Figure 7–22. PWT Block Diagram MPU peripheral bus TIPB interface Param 5-bit counter comparator 50/63 49/55 80/127 101/107 PWT_CLK t128 Tone & 1/154 Testin 7.7.3 PWT Registers Start address (hex): FFFB6000 Table 7–44 lists the PWT registers. Table 7–45 through Table 7–47 describe the individual registers.
Page 416: Pwt Frequency Control Register (Frc)
Pulse-Width Tone Table 7–45. PWT Frequency Control Register (FRC) – Offset address (hex): 0x00 Reset Name Function Value 5–2 Frequency selection (12 frequencies) 0000 Resynchronized writing, asynchronous reading 1–0 Octave selection Resynchronized writing, asynchronous reading Table 7–46. PWT Volume Control Register (VRC) – Offset address (hex): 0x04 Reset Name Function...
Page 417: Buzzer Frequencies
Pulse-Width Tone The clock behind the multiplexer is divided by 154 to get the required frequen- cies on the TONE output. The 12 frequencies in an octave can be programmed with bits 5 to 2 of the frequency control register (FRC), and the octave can be programmed with bits 1 to 0 of the FRC.
Page 418: Buzzer Volume
322 Hz 11XX XX Not allowed Note: The PWT was originally designed for a 13-MHz input clock, but the OMAP5910 device implements PWT with a 12-MHz clock. Consequently, frequencies shown are not exact tones. 7.7.4.2 Buzzer Volume The buzzer volume can be programmed (see Table 7–49) with bits 6 to 1 in the volume control register VRC.
Page 419: I2C System Overview
C controller function does support the multimaster mode, to which more than one device capable of controlling the bus can be connected. Including the OMAP5910, each I C device is recog- nized by a unique address and can operate as either transmitter or receiver depending on the function of the device.
Page 420: Signal Pads
C via the serial data pin (SDA) and the serial clock pin (SCL). These two wires carry information be- tween the OMAP5910 device and others connected to the I C bus. Both SDA and SCL are bidirectional pins. They must be connected to a positive supply voltage via a pullup resistor.
Page 421: Start And Stop Conditions
Inter-Integrated Circuit Controller 7.8.1.3 C Bus Base Principal The data on the SDA line must be stable during the high period of the clock. The high and low states of the data line can only change when the clock signal on the SCL line is low (see Figure 7–24).
Page 422 Inter-Integrated Circuit Controller 7.8.1.4 C Operation Serial Data Formats Each byte put on the SDA line is 8 bits long. The number of bytes that can be transmitted or received is unrestricted. The data is transferred with the most significant bit (MSB) first. Each byte is followed by an acknowledge bit from the module I C if it is in receiver mode (see Figure 7–26).
Page 423: I2C Data Transfer Formats
Inter-Integrated Circuit Controller Figure 7–27. I C Data Transfer Formats Slave Address Data Data (a) 7-Bit Addressing Format Slave Address 1st 7-Bit Slave Address 2nd 7-Bit Data 1 1 1 1 0 X X (Write) (b) 10-Bit Addressing Format Slave Address R/W ACK Data Slave Address...
Page 424: Arbitration Procedure Between Two Master Transmitters
Inter-Integrated Circuit Controller out on the data line SDA in synchronism with the clock pulses that are gener- ated by the master device. It does not generate the clock, but it can hold the clock line SCL low while intervention of the local host is required. Slave Receiver In this mode serial data bits received on the bus line SDA are shifted-in synchronously with the clock pulses on SCL, which are generated by the...
Page 425 Inter-Integrated Circuit Controller C Clock Generation and I C Clock Synchronization Under normal conditions, only one master device generates the clock signal, SCL. During the arbitration procedure, however, there are two or more master devices and the clock must be synchronized so that the data output can be compared.
Page 426 Inter-Integrated Circuit Controller 7.8.2 OMAP5910 I C (Master/Slave I C Controller) The multimaster I C peripheral provides an interface between TIPB bus and any I C-bus compatible devices that connect via the I C serial bus. External components attached to the I...
Page 427: Prescale Sampling Clock Divider Value
Inter-Integrated Circuit Controller 7.8.2.2 Data Format The I C controller operates in 16-bit word data format (byte write access supported for the last access), and it supports endianism. 7.8.2.3 C Reset The I2C_EN bit in the I C configuration register (I2C_CON) can also reset the C module.
Page 428 Inter-Integrated Circuit Controller A no-acknowledge interrupt (NACK) is generated when the master I C does not receive an acknowledge from the receiver. A registers-ready-for-access interrupt (ARDY) is generated by the I C when the previously programmed address, data and command have been per- formed and the status bits has been updated.
Page 429: I2C Registers
Inter-Integrated Circuit Controller 7.8.2.7 C Registers Table 7–52 lists the I C registers. Table 7–53 through Table 7–71 describe the register bits. Table 7–52. I C Registers Offset Register Description Access Address I2C_REV C module version 0x00 I2C_IE C interrupt enable 0x04 I2C_STAT C status...
Page 430 Inter-Integrated Circuit Controller The four MSBs indicate a major revision. Ex: 0x10: version 1.0 0x11: version 1.1 A reset has no effect on the value returned. Table 7–53. I C Module Version Register (I2C_REV) Name Description 15 –8 – Reserved 7 -0 Module version number The read/write I...
Page 431 Inter-Integrated Circuit Controller The read-only I C status register (I2C_STAT) provides core status information for interrupt handling and other I C control management. This register is always read before reading the I2C_IV register itself to retain an accurate status (some bits are cleared following a read into I2C_IV). Table 7–55.
Page 432 Inter-Integrated Circuit Controller Bus Busy (BB) This read-only bit (12) indicates the state of the serial bus. In the slave mode, on reception of a start condition, the device sets BB to 1. BB is clear to 0 after reception of a stop condition. In the master mode, the software controls BB.
Page 433 Inter-Integrated Circuit Controller XUDF is set to 1 when the I C has recognized an underflow. The core holds the line till the underflow cause has disappeared. XUDF is clear when writing I2C_DATA register or resetting the I (I2C_EN=0). 0: Normal operation 1: Transmit underflow Value after reset is low.
Page 434 Inter-Integrated Circuit Controller Transmit Data Ready (XRDY) Transmit mode only. XRDY (bit 4) is set to 1 when I C peripheral is a master or slave transmitter, the local host is able to write a new data into the I2C_DATA register, and the transmitter still requires a new data.
Page 435: Register Access Ready (Ardy) Set Conditions
Inter-Integrated Circuit Controller Register Access Ready (ARDY) This bit (2) when set to 1 indicates that the previously programmed data and command (receive or transmit, master or slave) have been performed and the status bit has been updated. This flag is used by the local host to let it know that the I C registers are ready to be accessed again.
Page 436 Inter-Integrated Circuit Controller 2) Write to the STP bit in the I2C_CON register to realse I C data line. Do not poll the NACK and AL bits in the I2C_CON register because an up- date could be missed. These bits require an interrupt process to be han- dled correctly (also, the INTCODE field in the I2C_IV register should be read before any action is taken in the subroutine).
Page 437: Interrupt Code (Intcode) Conditions
Inter-Integrated Circuit Controller Table 7–58. Interrupt Code (INTCODE) Conditions Interrupt Code Interrupt Occurred Priority None – Arbitration lost interrupt Highest ↓ No acknowledgement interrupt/general call Register access ready interrupt Receive data ready interrupt Transmit data ready interrupt Lowest Others Reserved –...
Page 438 Inter-Integrated Circuit Controller Table 7–60. I C Data Counter Register (I2C_CNT) Name Description 15–0 DCOUNT Data count Data Count (DCOUNT) Master mode only (receive or transmit). This 16-bit countdown counter decrements by 1 for every byte received or sent. A write initializes DCOUNT to a saved initial value. A read returns the number of bytes that are yet to be received or sent.
Page 439 Inter-Integrated Circuit Controller The I C data access register (I2C_DATA) is the entry point for the local host to read data from, or write data into, the FIFO buffer. The FIFO size is 2x16bits (4 bytes). Bytes within a word are stored and read in little endian format (I2C_CON:BE=0) or big endian format (I2C_CON:BE=1).
Page 440 Inter-Integrated Circuit Controller Table 7–62. I C Configuration Register (I2C_CON) Name Description I2C_EN C module enable Big endian mode 13–12 Reserved Start byte mode (master mode only) Master/slave mode Transmitter/receiver mode (master mode only) Expand address 7 –3 Reserved Repeat mode (master mode only) Stop condition (master mode only) Start condition (master mode only) C Module Enable (I2C_EN)
Page 441 Inter-Integrated Circuit Controller 0: Little endian mode 1: Big endian mode Value after reset is low. Start Byte (STB) Master mode only. The start byte mode bit (11) is set to 1 by the local host to configure the I C in start byte mode (I2C_SA=00000001).
Page 442: Operating Modes
Inter-Integrated Circuit Controller Table 7–63. Operating Modes Operating Modes Slave receiver Slave transmitter Master receiver Master transmitter Expand Address (XA) When set, this bit (8) expands the address to 10-bit. 0: 7-bit address mode 1: 10-bit address mode Value after reset is low. Repeat Mode (RM) Mater mode only.
Page 443: Stt Settings
Inter-Integrated Circuit Controller Stop Condition (STP) Master mode only. This bit (1) can be set to a 1 by the local host to generate a stop condition. It is reset to 0 by the hardware after the stop condition has been generated. The stop condition is generated when DCOUNT passes 0.
Page 444 Inter-Integrated Circuit Controller The I C own address register (I2C_OA) specifies the module I C 7-bit or 10-bit address (own address). Table 7–66. I C Own Address Register (I2C_OA) Name Description 15–10 Reserved 9 –0 Own address This field (bits 9-0) specifies either: A 10-bit address coded on OA[9:0] when XA (expand address, I2C_MCR[8]) is set to 1.
Page 445 Inter-Integrated Circuit Controller This register is used to specify the internal clocking of the I C peripheral core. Table 7–68. I C Clock Prescaler Register (I2C_PSC) Name Description 15–8 Reserved 7 –0 Prescale sampling clock divider value The core (bits 7-0) uses this 8-bit value to divide the peripheral clock (MPUXOR_CK) to generate its own internal sampling clock (ICLK).
Page 446 Inter-Integrated Circuit Controller The I C SCL high-time control register (I2C_SCLL) determines the SCL high- time value when master. Table 7–70. I C SCL High Time Control Register (I2C_SCLH) Name Description 15–8 Reserved 7–0 SCLH SCL high time Master mode only. This 8-bit value (bits 7-0) is used to generate the SCL high time value (t HIGH when the peripheral is operated in master mode.
Page 447: Tmode Settings
Inter-Integrated Circuit Controller System Test Enable (ST_EN) This bit (15) must be set to 1 to permit other system test registers bits to be set. 0: Normal mode 1: System test enabled Value after reset is low. Free Running Mode After Breakpoint (FREE) This bit (14) is used to determine the state of the I C controller when a break- point is encountered in the HLL debugger.
Page 448 Inter-Integrated Circuit Controller Values after reset are low (2 bits). In SCL counter test mode, the SCL pin is driven with a permanent clock as if master with the parameters set in I2C_PSC, I2C_SCLL, and I2C_SCLH registers. Loopback mode: In the master transmit mode only, data transmitted out of the I2C_DATA register (write action) is received in the same I2C_DATA register via an internal path through the 1-deep FIFO buffers.
Page 449: Programming
Inter-Integrated Circuit Controller SDA Line Drive Output Value (SDA_O) In normal functional mode (ST_EN = 0), this bit (0) is don’t care, and always reads as 0. Writes are ignored. In system test mode (ST_EN = 1 and TMODE = 11), a 0 forces a low level on the SDA line and a 1 puts the I C output driver in a high-impedance state.
Page 450: Setup Procedure
Inter-Integrated Circuit Controller Poll receive data: Poll the receive data ready interrupt flag bit (RRDY) in the I C status register (I2C_STAT), use the RRDY interrupt, or use the DMA to read the receive data in the data receive register (I2C_DATA). Poll transmit data: Poll the transmit data ready interrupt flag bit (XRDY) in the I C status register (I2C_STAT), use the XRDY interrupt, or use the...
Page 451: Master Transmitter Mode, Rm = 1
Inter-Integrated Circuit Controller Figure 7–32. Master Transmitter Mode, RM = 1 Start Read I 2 C_STAT. bus free send data (BB=0) being requested (XUDF=1) Write I 2 C_CON With 8605h. m bytes transferred n = 0 (data byte counter): (n. = m) m = Number of data bytes to be transferred n = n + 2...
Page 452: Master Receiver Mode, Rm = 1, Polling
Inter-Integrated Circuit Controller Figure 7–33. Master Receiver Mode, RM = 1, Polling 1 (Software Counter, Number of the Receive Data Fixed) Start Set appropriate values to every bit of I 2 C_CON. I 2 C_EN bit must be set Read I 2 C_STAT. to 1 to take I 2 C out of reset condition.
Page 453: Master Receiver Mode, Rm =1 , Polling
Inter-Integrated Circuit Controller Figure 7–34. Master Receiver Mode, RM =1 , Polling 2 (Number of the Receive Data is Variable, Data Contents Dependent) Start Read I 2 C_STAT. received data bus free in I 2 C_DATA (BB=0) (RRDY=1) Write I 2 C_CON Read I 2 C_DATA.
Page 454: Master Transmitter Mode, Rm
Inter-Integrated Circuit Controller Figure 7–35. Master Transmitter Mode, RM = 0, Polling [EXPECTED COMMAND] Start At the beginning, (STT,STP) = (1.0), (1.1), (1.0), (1.1) Read I 2 C_STAT. in the middle, (STT, STP) = (0.0), (0.1) At the end, (STT, STP) = (0.1) Bus free (BB=0) [EXPECTED I 2 C_IE]...
Page 455: Master Receiver Mode, Rm = 0, Polling
Inter-Integrated Circuit Controller Figure 7–36. Master Receiver Mode, RM = 0, Polling [EXPECTED COMMAND] Start At the beginning, (STT,STP) = (1.0), (1.1), (1.0), (1.1) Read I 2 C_STAT. in the middle, (STT, STP) = (0.0), (0.1) At the end, (STT, STP) = (0.1) Bus free (BB=0) [EXPECTED I 2 C_IE]...
Page 456: Master Transmitter Mode, Rm = 0, Interrupt
Inter-Integrated Circuit Controller Figure 7–37. Master Transmitter Mode, RM = 0, Interrupt [EXPECTED COMMAND] Start At the beginning, (STT,STP) = (1.0), (1.1), (1.0), (1.1) Read I 2 C_STAT. in the middle, (STT, STP) = (0.0), (0.1) At the end, (STT, STP) = (0.1) Bus free (BB=0) [EXPECTED I 2 C_IE]...
Page 457: Master Receiver Mode, Rm = 0, Interrupt
Inter-Integrated Circuit Controller Figure 7–38. Master Receiver Mode, RM = 0, Interrupt [EXPECTED COMMAND] Start At the beginning, (STT,STP) = (1.0), (1.1), (1.0), (1.1) Read I 2 C_STAT. in the middle, (STT, STP) = (0.0), (0.1) At the end, (STT, STP) = (0.1) Bus free (BB=0) [EXPECTED I 2 C_IE]...
Page 458: Master Transmitter Mode, Rm = 0, Dma
Inter-Integrated Circuit Controller Figure 7–39. Master Transmitter Mode, RM = 0, DMA [EXPECTED COMMAND] At the beginning, Start (STT,STP) = (1.0), (1.1), (1.0), (1.1) in the middle, (STT, STP) = (0.0), (0.1) Read I 2 C_STAT. At the end, (STT, STP) = (0.1) [EXPECTED I 2 C_IE] Bus free I 2 C_IE = 00111b...
Page 459: Master Receiver Mode, Rm = 0, Dma
Inter-Integrated Circuit Controller Figure 7–40. Master Receiver Mode, RM = 0, DMA [EXPECTED COMMAND] At the beginning, Start (STT,STP) = (1.0), (1.1), (1.0), (1.1) in the middle, (STT, STP) = (0.0), (0.1) Read I 2 C_STAT. At the end, (STT, STP) = (0.1) [EXPECTED I 2 C_IE] Bus free I 2 C_IE = 00111b...
Page 460: Slave Transmitter/Receiver Mode, Polling
Inter-Integrated Circuit Controller Figure 7–41. Slave Transmitter/Receiver Mode, Polling Start Read I C_STAT. Write data Read data (XRDY=1) (RRDY=1) Read I C_DATA. Write I C_DATA. 7-98...
Page 461: Slave Transmitter/Receiver Mode, Interrupt
Inter-Integrated Circuit Controller Figure 7–42. Slave Transmitter/Receiver Mode, Interrupt Start interrupt received Read I C_IV. Transmit Receive C_IV=5) C_IV=4) Write I C_DATA. Read I C_DATA. MPU Public Peripherals 7-99...
Page 462: Led Pulse Generator Block Diagram
The LED pulse generator (LPG) module controls an indication LED (see Figure 7–43). The blinking period is programmable between 152 ms and 4s, and the LED can be switched on permanently. The OMAP5910 device has two LPG modules. Each LPG module drives a single output pin on the OMAP5910 device which can be used to switch an LED driver.
Page 463: Led Pulse Generator Receive And Transmit Registers
The LPG input clock comes from the 32-kHz ULPD clock, because it must work even when the OMAP5910 system is in deep sleep mode. The internal clock of the LPG runs with 256 Hz. For this reason the power consumption of this block can be neglected.
Page 464: Lpg Control Register (Lcr)
LED Pulse Generator Table 7–74. LPG Control Register (LCR) Reset Name Function Value PERM_ON Set high to force permanent light on. Asynchronous writing and reading. LPGRES LPG counter reset, active low. Asynchronous writing and reading. 5–3 ONCTRL Time LED is on parameter. Asynchronous writing and reading.
Page 465: Led On Time
LED Pulse Generator With the LCR bits 5-3, the on time of the LED is determined. Table 7–76. LED On Time LCR Bit 5 LCR Bit 4 LCR Bit 3 Time LED On Number of Clock Cycles 3.889 ms 7.789 ms 15.59 ms 31.39 ms 46.59 ms...
Page 466: Mcbsp2
Multichannel buffered serial ports (McBSPs) are configurable, high-speed, full-duplex serial ports that allow direct interfacing to external communication devices. There are three McBSPs on OMAP5910. McBSP2 is on the MPU public peripheral bus and is covered briefly in this section. McBSP1 and McBSP3 are on the DSP public peripheral bus and are covered briefly in Chapter 9, DSP Public Peripherals.
Page 467: Mcbsp2 Pin Descriptions
McBSP2 Table 7–78 describes the McBSP2 pins. Table 7–79 lists the McBSP2 regis- ters. Figure 7–44 shows the McBSP2 interface. Table 7–78. McBSP2 Pin Descriptions I/O Direction Description MCBSP2.CLKR In/out Receive clock MCBSP2.CLKX In/out Transmit clock MCBSP2.DR Data input MCBSP2.DX Data output MCBSP2.FSR In/out...
Page 468 McBSP2 Table 7–79. McBSP2 Registers (Continued) Name Description Offset RCERA (15:0) Receive channel enable register partition A 0x1C RCERB (15:0) Receive channel enable register partition B 0x1E XCERA (15:0) Transmit channel enable register partition A 0x20 XCERB (15:0) Transmit channel enable register partition B 0x22 PCR0(15:0) Pin control register...
Page 469: Mcbsp2 Interface Diagram
McBSP2 Figure 7–44. McBSP2 Interface Diagram OMAP5910 McBSP2 TX (DMA_REQ_16) System CLKS MPUPER_CK RX (DMA_REQ_17) requests MCBSP2.FSX FSX_OUT TX interrupt (level 1 FSX_OE IRQ_4) FSX_IN RX interrupt (level 1 IRQ_5) MCBSP2.CLKX CLKX_OUT Interrupts CLKX_OE interrupt handler CLKX_IN RX overflow (level 2 MCBSP2.DX...
Page 470: Communication Processor Data Interface
The active input clock can be changed in a McBSP register, but register activity on CLKS is required to perform the set up and write to the McBSP. Figure 7–45. Communication Processor Data Interface OMAP5910 Communication processor MPU peripheral...
Page 471: Pin Control Register Configuration
CLKX set output pin and driven by internal generator CLKR set input pin and derived by external source Sample rate generator input clock mode bit CLKS pin status (no meaning in the OMAP5910 device) DX pin status DR pin status...
Page 472: Receive Control Register 1 Configuration
McBSP2 7.10.1.3 Receive Control Register Configuration ARM_Write(0x0040) => RCR1; set up RCR1 per below configuration. Table 7–81. Receive Control Register 1 Configuration Configuration Value Description Reserved 14–8 000 0000b Set receive frame length as one word per frame 7–5 010b Set receive word length as 16 bit per frame 4–0 0 0000b...
Page 473: Transmit Control Register 2 Configuration
McBSP2 ARM_Write(0x0001) => XCR2; set up XCR2 per below configuration. Table 7–84. Transmit Control Register 2 Configuration (ARM_Write(0x0001) => XCR2) Configuration Value Description Set single-phase frame 14–8 000 0000b Don’t care for single-phase frame 7–5 000b Don’t care for single-phase frame 4–3 Set no companding data and transfer start with MSB first Set FSX not ignore after the first resets the transfer...
Page 474: Waveform Example
McBSP2 7.10.1.8 Transmit Data Loading (TX_INT Handling in Interrupt Survive Routine) ARM_Write → DXR Note: Clear interrupts flag on ITR, when taken the interrupt handle. 7.10.1.9 Received Data Loading (RX_INT Handling in Interrupt Survive Routine) ARM_Read ← DRR Note: Clear interrupts flag on ITR, when taken the interrupt handle. Waveform Example Figure 7–46.
Page 475: Pin Control Register Configuration
CLKX set output pin and driven by internal generator CLKR set input pin and derived by external source Sample rate generator input clock mode bit CLKS pin status (no meaning in OMAP5910) DX pin status DR pin status Set FSX polarity as active high...
Page 476: Receive Control Register 1 Configuration
McBSP2 7.10.1.12 Receive Control Register Configuration ARM_Write(0x0040) => RCR1; set up RCR1 per below configuration. Table 7–86. Receive Control Register 1 Configuration Configuration Description Value Reserved 14–8 000 0000b Set receive frame length as one word per frame 7–5 010b Set receive word length as 16 bits per frame 4–0 0 0000b...
Page 477: Transmit Control Register 2 Configuration
McBSP2 ARM_Write(0x0001) => XCR2; set up XCR2 per below configuration. Table 7–89. Transmit Control Register 2 Configuration Configuration Value Description Set single-phase frame 14–8 000 0000b Don’t care for single-phase frame 7–5 000b Don’t care for single-phase frame 4–3 Set no companding data and transfer start with MSB first Set FSX not ignore after the first resets the transfer 1–0 Set data delay as 1 bit...
Page 478: Waveform Example
McBSP2 7.10.1.18 Data Transfer (DMA Channel) The DMA channel transfers the received data to appropriate data buffer and transfer the new transmit data to appropriate TX buffer. Clear interrupts flag on ITR, when taking the interrupt handle. Note: Clear interrupts flag on ITR, when taken the interrupt handle. Waveform Example Figure 7–47.
Page 479: Usb Function Registers
USB Function Overview 7.11 USB Function Overview The universal serial bus (USB) function module supports the implementation of a full-speed device fully compliant with the USB 1.1 standard (see Figure 13–2). It provides an interface between the MPU core (TI925T) and the USB wire and handles USB transactions with minimal TI925T intervention.
Page 480 USB Function Overview Table 7–90. USB Function Registers (Continued) Offset Name Description Address DMA_IRQ_EN Enables all DMA interrupts 0x2C IRQ_SRC Identify and clear the source of the interrupt signaled by a set flag 0x30 EPN_STAT Identify the non-ISO endpoint causing an EPn interrupt 0x34 DMAN_STAT Identify the endpoint causing a DMA interrupt...
Page 481 USB Function Overview Table 7–90. USB Function Registers (Continued) Offset Name Description Address Endpoint Configuration Gives the device configuration for control endpoint 0 EP1_RX Gives the device configuration for non-control receive endpoint 1 0x84 EP2_RX Gives the device configuration for non-control receive endpoint 2 0x88 …...
Page 482: Mmc/Sd Host Controller Environment
MMC/SD Host Controller 7.12 MMC/SD Host Controller The MMC/SD host controller provides an interface between the TI925T and either MMC or SD memory card plus up to three serial flash cards and handles MMC/SD or SPI transactions with minimal TI925T intervention. All references to a local host in this section refer to the TI925T MPU processor.
Page 483 LATCH static_valid OMAP5910 CONFIGURATION MMC/SD CONF_MMC dma_rd_req_oqn System DMA DMA_REQ[21] MOD_CONF_CTRL_0(32) MMC card MMC card Nrespwron dma_wr_req_oqn Dat[0] Dat[0] DMA_REQ[20] Functional multiplexing adp_clk_o MPU Interrupt Handler Lev2 irq_oqn MMC_CLK adp_clock_i Irq23 VDDSHV6 adp_rcmd_o adp_cmd_dir_oq adp_cmd_oq adp_cmd_i MMC_CMD (SPI_SO) VDDSHV6 adp_rdat_o...
Page 484: Mmc/Sd Host Controller Features
The state of the OMAP5910 static_valid input during power on, determines the functional multiplexing on the OMAP5910 MMC/SD pads. The OMAP5910 static_valid pad must be held to 1 during power on so that the MMC/SD host controller signals are usable from the power-on reset on the OMAP5910 MMC/SD pads (described in Table 7–91).
Page 485: Mmc/Sd Signal Pads
MMC/SD Host Controller Table 7–91. MMC/SD Signal Pads Pullup/ Reset Pad Name Type Description Pulldown Value MMC.CLK MMC/SD card CLK signal. Only active during active command to a MMC/SD card using MMC or SPI protocols. MMC.CMD_SPI. In-Out Pullup Input MMC/SD card CMD signal in MMC/SD mode. DO/SPI_SO (*3) SPI serial out signal in SPI mode (output—goes to serial...
Page 486: Mmc/Sd Host Controller Clocks And Reset
MMC/SD Host Controller 7.12.3 MMC/SD Host Controller Clocks and Reset The MMC/SD host controller has two clocks: An interface clock (clock_i) used between the MPU TIPB and the MMC/SD host controller and connected to the MPU peripheral programmable clock (PERCLK), is determined dividing CK_GEN1 (the output of DPLL1) by the value associated with the PERDIV field of the ARM_CKCTL register (0xFFFECE00).
Page 487: Mmc_Dat Pullups
MMC/SD Host Controller 7.12.6 MMC/SD Internal Pullups There are internal pullups on the following pins: MMC.CMD I/O pin MMC.DAT[3:0] I/O pins MMC cards work in open drain mode on the MMC.CMD line during the identifi- cation phase, and more generally for broadcast MMC commands; con- sequently, a pullup on the MMC.CMD line is needed.
Page 488: Mmc/Sd Registers
MMC/SD Host Controller 7.12.7 MMC/SD Registers Table 7–94 lists the MMC/SD controller registers. Table 7–95 through Table 7–122 describe the register bits. Table 7–94. MMC/SD Registers Register Description Access Address MMC_CMD MMC command FFFB:7800 MMC_ARGL MMC argument low FFFB:7804 MMC_ARGH MMC argument high FFFB:7808 MMC_CON...
Page 489: Mmc Command Register (Mmc_Cmd)
MMC/SD Host Controller Table 7–95. MMC Command Register (MMC_CMD) Name Description DDir Data direction [read/write] Stream command or broadcast host response 13 –12 Type Command types [bc,bcr,ac,adtc] Busy Command with busy response [R1b] 10– 8 Response Command responses [no response, R1/R1b, R2, R3, R4, R5,R6] Init Send initialization stream Card open drain mode...
Page 490 MMC/SD Host Controller Stream Command or Broadcast Host Response (SHR) MMC card only. SD card does not support stream operation or host generated response. This bit (14) must be set to 1 in two cases: Associated with adtc type, if the command is a stream data transfer (read or write).
Page 491 MMC/SD Host Controller Command With Busy Response (Busy) This bit (11) must be set to 1 if the response to the command sent is of type R1b (R1 + busy). 0: Response without busy (R1, R2, R3, R4, R5, R6) 1: Response with busy (R1b) Value after reset is low.
Page 492: Mmc Argument Low Register (Mmc_Argl)
MMC/SD Host Controller Card Open Drain Mode (OD) This bit (6) must be set to 1 if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode, the card is either in idle, ready or identification state. This bit must be set for MMC card commands 1, 2, 3, and 40.
Page 493: Mmc System Configuration Register (Mmc_Con)
MMC/SD Host Controller Table 7–98. MMC System Configuration Register (MMC_CON) Name Description Data bus width Reserved 13–12 Mode Operating mode select (MMC/SD, SPI, SYSTEST, or MMC SPI protocol). Power-up Power-up control 10 –8 Reserved 7 –0 Clk_div Clock divider [No clock, 1:255] Bus Width During Data Phase (DW) SD card only.
Page 494 MMC/SD Host Controller In SPI mode 2, transfers to the MMC/SD card follow the SPI protocol. MMC clock is enabled and the SPI clock is disabled. MMC protocol must be imple- mented in software when using this mode since the MMC interface acts as a generic SPI port and does not utilize the MMC-specific features available in MMC/SD mode.
Page 495: Clock Control
MMC/SD Host Controller Clock Divider (Clk_div) These bits (7-0) define the ratio between a reference clock frequency (48 MHz) and the output clock frequency on the CLK pin of either the memory card (MMC or SD) or other 8-bit mode SPI controlled device. The division factor is exactly the binary encoded decimal value for values between 1 and 255.
Page 496: Mmc_Clk/Spi_Clk High-/Low-Time Computation
MMC/SD Host Controller Table 7–99. MMC_CLK/SPI_CLK High-/Low-Time Computation Clk_Div MMC_CLK/SPI_CLK High-Time MMC_CLK/SPI_CLK Low-Time ref_clk_high_time ref_clk_low_time Even ≥ 2 ref_clk_per (Clk_div/2) ref_clk_per (Clk_div/2) Odd ≥ 3 ref_clk_per (TRUNC[Clk_div/2] + 1) ref_clk_per (TRUNC[Clk_div/2]) (POL=PHA) Odd ≥ 3 ref_clk_per (TRUNC[Clk_div/2]) ref_clk_per (TRUNC[Clk_div/2] + 1) (POL≠PHA) ref_clk_per is reference clock period (in ns) to the module (end-system dependant).
Page 497: Mmc System Status Register (Mmc_Stat)
MMC/SD Host Controller Table 7–100. MMC System Status Register (MMC_STAT) Name Description Reserved Card_Err Card status error in response Card_IRQ Card IRQ received (following CMD40) OCR_busy OCR busy (following CMD1 or ACMD41) A_Empty Buffer almost empty A_Full Buffer almost full Reserved Cmd_CRC Command CRC error...
Page 498: Response Types
MMC/SD Host Controller Table 7–101. Response Types Card Status Bits With Response Response Register Error Type Significant Bits Comments R1 (MMC, 31-26, 24-16, MMC_RSP7[15:10,8-0] These 15 bits can all generates errors. 3* (opt) MMC_RSP6[3] This bit can also generate an error if enabled (bit 3 if MMC_SDIO[13]=1) per the SD application specification R6 (SD)
Page 499 MMC/SD Host Controller OCR Busy (OCR_busy) MMC/SD mode only. The core automatically sets this bit (12) after a SEND_OP_COND (CMD1) or a SD_APP_OP_COND (ACMD41) command when one or more cards have not yet completed power up. When this bit is set, the CMD1/ACMD41 com- mand must be repeated until the card stops responding with a busy condition.
Page 500 MMC/SD Host Controller Buffer Almost Full (A_Full) The core automatically sets this bit (10) during a read operation to the card when the level is above the threshold value set in MMC_BUFF:AF_Level reg- ister bits. This bit indicates that the memory card has filled out the buffer to the specified level and that the local host needs to empty the buffer by reading it.
Page 501 MMC/SD Host Controller In SPI or SYSTEST modes, this bit has no meaning and always reads as 0. 0: No action or no command time-out 1: Command time-out Value after reset is low. Data CRC Error (Dat_CRC) MMC/SD mode only. The core automatically sets this bit (6) if there is CRC16 error in the data phase response following a block read command (single or multiple) or if there is a 3-bit CRC status token error 101 to signal for data transmission error during...
Page 502 MMC/SD Host Controller Card Exit Busy State (EOF_Busy) MMC/SD mode only. The core automatically sets this bit (4) when the addressed card releases the DAT line from its busy state (low level = busy). This bit can only get set during a programming phase (write operation) to a MMC or SD memory card.
Page 503 MMC/SD Host Controller Card Enter Busy State (Card_Busy) MMC/SD mode only. The core automatically sets this bit (2) when the addressed card asserts the DAT line to a low level during a programming phase (write operation) to a MMC or SD memory card. For the MMC card only, the user can optionally use this interrupt to deselect the card (which continues to program) and select another card.
Page 504: Mmc System Interrupt Register (Mmc_Ie)
MMC/SD Host Controller Table 7–102. MMC System Interrupt Register (MMC_IE) Name Description Reserved Card_Err_IE Card status error interrupt enable Card_IRQ_IE Card IRQ interrupt enable OCR_busy_IE OCR busy interrupt enable A_Empty_IE Buffer almost empty interrupt enable A_Full_IE Buffer almost full interrupt enable Reserved Cmd_CRC_IE Command CRC error interrupt enable...
Page 505: Mmc Command Time-Out Register (Mmc_Cto)
MMC/SD Host Controller The 16-bit MMC command time-out register (MMC_CTO) specifies the maximum number of clock cycles before a command time-out condition occurs. Table 7–103. MMC Command Time-out Register (MMC_CTO) Name Description 15 –8 Reserved 7–0 MMC command time-out value. Command Time-out Value (CTO) MMC/SD mode only.
Page 506: Data Time-Out Conditions
MMC/SD Host Controller This 16-bit register specifies the maximum number of clock cycles before a data time-out condition occurs. Table 7–104. MMC Data Time-out Register (MMC_DTO) Name Description 15–0 Data read time-out Data Time-out Value (DTO) In MMC/SD mode, the local host sets this field (bits 15-0) based on N clock cycles.
Page 507: Mmc Data Access Register (Mmc_Data)
MMC/SD Host Controller The MMC data access register (MMC_DATA) is the entry point for the local host to read data from, or write data into, the FIFO buffer. The FIFO size is 32 x 16bits (64 bytes). Bytes within a word are stored and read in little endian format.
Page 508: Mmc Block Length Register (Mmc_Blen)
MMC/SD Host Controller This register configures the core for the number of bytes to read or write. It must be initialized at least once prior to starting an MMC, SD, or SPI block data transfer (read or write). Table 7–107. MMC Block Length Register (MMC_BLEN) Name Description 15–11...
Page 509: Mmc Number Of Blocks Register (Mmc_Nblk)
MMC/SD Host Controller This register configures the number of blocks for a multiple block data transfer (read or write) operation for MMC/SD cards. This register is not used for SPI transfers. Table 7–108. MMC Number of Blocks Register (MMC_NBLK) Name Description 15–11 Reserved...
Page 510: Mmc Buffer Configuration Register (Mmc_Buf)
MMC/SD Host Controller This register configures the buffer threshold level of the thirty two 16-bit-word FIFO and enables DMA transfers. Table 7–109. MMC Buffer Configuration Register (MMC_BUF) Name Description RX_DMA_En Receive DMA channel enable 14 –13 Reserved 12 –8 AF_Level Buffer almost full level TX_DMA_En Transmit DMA channel enable...
Page 511 MMC/SD Host Controller Transmit DMA Channel Enable (TX_DMA_En) When this bit (7) is set to 1, the transmit DMA channel is enabled and the A_Empty status bit is forced to 0 by the core irrespectively of AE_level setting (see Table 7–109). More information regarding DMA operation can be found in Chapter 5, System DMA Controller.
Page 512: Mmc Spi Configuration Register (Mmc_Spi)
MMC/SD Host Controller This register is used to configure the SPI interface and start an SPI transfer if SPI mode has been enabled. Table 7–110. MMC SPI Configuration Register (MMC_SPI) Name Description Start Start SPI transfer Write/not read 13 –12 Reserved 11 –10 TCSH...
Page 513 MMC/SD Host Controller Write/Not Read (WnR) This bit (14) instructs the 11-bit block length counter in MMC_BLEN:BLEN to decrement either on byte read when WnR = 0 or on byte write when WnR = 1. 0: Decrement on byte received 1: Decrement on byte sent Value after reset is low.
Page 514: Spi Mode C/S Timings Controls (Pol = 0)
MMC/SD Host Controller Figure 7–50. SPI Mode C/S Timings Controls (POL = 0) SPI shift clock (module generated Internal clock) SPI_CLK (POL=0) SPI_CSn[3:0] TCSS = 1 TCSH = 0.5 TCSS = 2 TCSH = 1.5 TCSS = 3 TCSH = 2.5 TCSS = 4 TCSH = 3.5 Figure 7–51.
Page 515: Chip-Select Control (Spi Mode)
MMC/SD Host Controller Chip-Select Mode (CSM) When this bit (3) is set to 0 and enabled (CSD=0), the selected CS signal pin goes active (low) only when SPI transfer is started and brought back automati- cally to its inactive state (high), when the SPI transfer completes. When set to 1, the automatic control of the CS signal is disabled.
Page 516 MMC/SD Host Controller Clock Phase (PHA) The clock polarity and clock phase bits select four different clocking schemes for the SPICLK pin. The clock phase bit (1) selects a half cycle delay for clock. When clock phase = 0: MSB data is ready one half cycle of SPICLK before the SPI clock starts. Data is shifted-in in reception on the first edge transition of SPICLK.
Page 517: Spi Master Configuration Bits
MMC/SD Host Controller Figure 7–52. SPI Master Configuration Bits SPI MASTER Configuration SPI Mode SPI_CLK SPI_CLK SPI_CLK SPI_CLK This register provides additional controls for the MMC/SD interface. It is also reserved for future SDIO operation (not supported in present version). Table 7–112.
Page 518: Mmc System Test Register (Mmc_Syst)
MMC/SD Host Controller Data Time-out Prescaler Enable (DTO_PS_En) When this bit (5) is set to 1 by the LH, the data time-out set in MMC_DTO regis- ter is x1024 the number of MMC_CLK cycles. 0: x1 (Prescaler off) 1: x1024 (Prescaler on) Value after reset is low.
Page 519 MMC/SD Host Controller Ready/Busy Data (RDY_dat) This read-only bit (13) returns the value of the signal on the input pad (high or low). 0: Ready/busy low 1: Ready/busy high Value after reset is high. DAT[3:0] Direction (DAT_dir) When set, this bit (12) places all the in/out DAT[3:0] pins in output mode. 0: Input 1: Output Value after reset is low.
Page 520: Mmc Module Version Register (Mmc_Rev)
MMC/SD Host Controller MMC_CLK Data (MMC_CK_dat) The MMC_CK pin is driven high or low according to the value written into this register bit (5). Value after reset is low. SPI_CLK Data (SPI_CK_dat) The SPI_CK pin is driven high or low according to the value written into this register bit (4).
Page 521: Mmc/Sd Command Response Register 0 (Mmc_Rsp0)
MMC/SD Host Controller Table 7–115 through Table 7–122 describe 16-bit registers that hold specified bits positions for a 128-bit response of type R2. Table 7–115. MMC/SD Command Response Register 0 (MMC_RSP0) Name Description 15 – 0 RESP0 CMD response (R2[15:0]) Table 7–116.
Page 522: Mmc/Sd Command Response Register 6 (Mmc_Rsp6)
MMC/SD Host Controller Table 7–121 and Table 7–122 describe registers that also hold specified bit positions for a 32-bit response of type R1/R1b/R3/R4/R5/R6. Table 7–121. MMC/SD Command Response Register 6 (MMC_RSP6) Name Description 15 –0 RESP6 CMD response (R2[111:96], R1/R1b/R3/R4/R5/R6[23:8]) Table 7–122.
Page 523: Command Flow
MMC/SD Host Controller 7.12.8 Command Flow To correctly drive the MMC/SD adapter for a command execution, the host must follow the process shown in Figure 7–53 and Figure 7–54. Figure 7–53. Command Flow Initialization (set system configuration) Operation without data Operation with data Set transfer parameters Send command...
Page 524: Initialization Phase
MMC/SD Host Controller Figure 7–54. Initialization Phase Host activity The user must set several registers Description Adapter activity Description Waiting IRQ by the host unit IRQ name In all modes (MMC, SD, SPI) a initialization phase is necessary at the begin- ning.
Page 525: Command Transfer
MMC/SD Host Controller Figure 7–56. Command Transfer Send command Write MMC_ARG1. (with type response direction) Write MMC_ARG2IE. Write MMC_CMD. Command time-out End of command Next operation When a command that has no response is used (that is, CMD0, CMD4, CMD15), the command timeout condition can never occur, since there is no response expected.
Page 526: Data Transfer
MMC/SD Host Controller Figure 7–57. Data Transfer Set transfer parameters Write MMC_BUF. Almost full/empty level and Rx/Tx DMA (if needed). Write MMC_BLEN. If the value does not change it is not useful to set it again. Write MMC_NBLK. – In single mode, NBLK must be = 0. –...
Page 527: Data Transfer In Mmc/Sd Mode Example
MMC/SD Host Controller Figure 7–58. Data Transfer in MMC/SD Mode Example Initialization (set system configuration) Set transfer parameters Read operation Write operation In multi-block the Send command MMC_NBLK(/=0) must be (with type response direction) set for every new operation. Send command (with type response direction) Write data buffer Blocks received from card...
Page 528: Dma Operation
MMC/SD Host Controller 7.12.9 DMA Operation 7.12.9.1 MMC DMA Receive Mode In a DMA block read operation (single or multiple): The DMA RX request signal is asserted to its active level when the FIFO level becomes equal or greater than the threshold set in AF_level. The DMA RX request is deasserted to its inactive level when the system DMA has read one word from the FIFO.
Page 529 MMC/SD Host Controller 7.12.9.2 MMC DMA Transmit Mode In a DMA block write operation (single or multiple): The DMA TX request signal is asserted to its active level when the FIFO level becomes less than the threshold set in AE_level after the block write command has been set (write action into MMC_CMD).
Page 530: Local Host (Irq/Polling) Mode
MMC/SD Host Controller 7.12.10 Local Host (IRQ/Polling) Mode 7.12.10.1 MMC Local Host (IRQ/Polling) Receive Mode During a local host block read operation (single or multiple) using inerrupt/poll- ing mode, the A_Full status bit is set active (high level) when the FIFO level becomes equal or greater than the threshold set in AF_level.
Page 531: Rtc Clock Diagram
Real-Time Clock 7.13 Real-Time Clock The real time clock (RTC) is an embedded module (see Figure 7–59). Its basic features are: Time information (seconds/minutes/hours) directly in BCD code Calendar information (day/month/year/day of the week) directly in BCD code up to year 2099 Interrupt generation, periodically (1s/1m/1h/1d period) or at a precise time of the day (alarm function) 30 s time correction...
Page 532: Time And Calendar Register Values
Real-Time Clock 7.13.1 Register Descriptions All the time and calendar information is available in dedicated registers, which are called time and calendar registers. Time and calendar register values are written in binary coded decimal (BCD) code (see Table 7–123). Table 7–123. Time and Calendar Register Values Time Unit Range Remarks...
Page 533: Time And Calendar Registers And Alarm Register Access
Real-Time Clock 7.13.2.1 Time and Calendar Registers/Alarm Registers To read or write correct data to and from the time and calendar registers/alarm registers, the MPU must first poll the BUSY bit of the STATUS register until BUSY is equal to zero. From this time, and for a time of 15 µs (the available access period), the MPU can safely access the time and calendar registers/ alarm registers.
Page 534 Real-Time Clock The RTC_DISABLE bit of the CTRL register must only be used to completely disable the RTC function. When this bit is set, the 32-kHz clock is gated, and the RTC is frozen. From this point, resetting this bit to zero can lead to unex- pected behavior.
Page 535: Compensation Scheduling
Real-Time Clock Figure 7–61. Compensation Scheduling Hours Seconds Load Load Comp Comp registers registers Compensation event Compensation event Hours COMP_EN Seconds Busy Load comps Hour event Compensation event Compensation scheduling MPU Public Peripherals 7-173...
Page 536: Irq Generation Waveform
Real-Time Clock 7.13.2.6 Interrupts Management RTC can generate two interrupts: Timer interrupt (IRQ_TIMER) Alarm interrupt (IRQ_ALARM_CHIP) 7.13.2.7 Timer Interrupt IRQ_TIMER interrupt can be generated periodically every second, every minute, every hour, or every day (RTC_INTERRUPTS_REG[1:0]). The IT_TIMER bit of the interrupt register enables this interrupt. The timer interrupt is a negative-edge-sensitive interrupt (low-level pulse duration = 15 µs).
Page 537: Irq Alarm Interrupt Waveform
Real-Time Clock 7.13.2.8 Alarm Interrupt IRQ_ALARM_CHIP interrupt can be generated when the time set into time and calendar alarm registers is exactly the same as in the time and calendar registers (see Figure 7–63). This interrupt is then generated if the IT_ALARM bit of the interrupts register is set.
Page 538: Positive And Negative Compensation Effect
Real-Time Clock Figure 7–64 summarizes positive and negative compensation effect. Figure 7–64. Positive and Negative Compensation Effect No compensation 32-kHz clock Timer counter 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 0000 0001 Second update Negative compensation: comp_reg = +2 32-kHz clock Timer counter 7FFA 7FFB...
Page 539: Rtc Registers
Real-Time Clock 7.13.3 Register Descriptions and Mapping Table 7–125 lists the RTC registers. Table 7–126 through Table 7–143 describe the register bits. Table 7–125. RTC Registers Base Offset Register Description Size Access Address Address SECONDS_REG Seconds 8 bits FFFB:4800 0x00 MINUTES_REG Minutes 8 bits...
Page 540: Seconds Register (Seconds_Reg)
Real-Time Clock Table 7–126. Seconds Register (SECONDS_REG) Reset Name Function Value Reserved 6–4 SEC1 digit of seconds Range is 0 to 5 3–0 SEC0 digit of seconds 0000 Range is 0 to 9 Table 7–127. Minutes Register (MINUTES_REG) Reset Name Function Value Reserved...
Page 541: Days Register (Days_Reg)
Real-Time Clock Table 7–129. Days Register (DAYS_REG) Reset Name Function Value 7–6 Reserved 5–4 DAY1 digit of days Range from 0 to 3 3–0 DAY0 digit of days 0001 Range from 0 to 9 Table 7–130. Months Register (MONTHS_REG) Reset Name Function Value...
Page 542: Alarm Seconds Register (Alarm_Seconds_Reg)
Real-Time Clock Table 7–133. Alarm Seconds Register (ALARM_SECONDS_REG) Reset Name Function Value Reserved 6–4 ALARM_SEC1 digit of seconds Range from 0 to 5 3–0 ALARM_SEC0 digit of seconds 0000 Range from 0 to 9 Table 7–134. Alarm Minutes Register (ALARM_MINUTES_REG) Reset Name Function...
Page 543: Alarm Days Register (Alarm_Days_Reg)
Real-Time Clock Table 7–136. Alarm Days Register (ALARM_DAYS_REG) Reset Name Function Value 7–6 Reserved 5–4 ALARM_DAY1 digit for days Range from 0 to 3 3–0 ALARM_DAY0 digit for days 0001 Range from 0 to 9 Table 7–137. Alarm Months Register (ALARM_MONTHS_REG) Reset Name Function...
Page 544: Rtc Control Register (Rtc_Ctrl_Reg)
Real-Time Clock Table 7–139. RTC Control Register (RTC_CTRL_REG) Reset Name Function Value Reserved † RTC_DISABLE RTC enabled RTC disabled (no 32-kHz clock) ‡ SET_32_COUNTER No action Sets the 32-kHz counter with COMP_REG (14:0) val- TEST_MODE Functional mode Test mode (autocompensation is enabled when 32-kHz counter reaches its end) §...
Page 545: Rtc Status Register (Rtc_Status_Reg)
Real-Time Clock Table 7–140. RTC Status Register (RTC_STATUS_REG) Reset Name Value Function Value † POWER_UP Indicates that a reset occurred ‡ ALARM Indicates that an alarm interrupt has been generated 1D_EVENT One day has occurred 1H_EVENT One hour has occurred 1M_EVENT One minute has occurred 1S_EVENT...
Page 546: Rtc Compensation Lsb Register (Rtc_Comp_Lsb_Reg)
Real-Time Clock Table 7–141. RTC Interrupts Register (RTC_INTERRUPTS_REG) (Continued) Reset Name Value Function Value 1–0 EVERY Interrupt period Every second Every minute Every hour Every day Note: The MPU must respect the busy period to prevent spurious interrupt. Table 7–142. RTC Compensation LSB Register (RTC_COMP_LSB_REG) Reset Name Function...
Page 547: Usb Host Controller Overview
USB Host Controller Overview 7.14 USB Host Controller Overview The OMAP5910 device implements a three-port USB host controller that is compatible with the USB Revision 1.1 specification and the Open Host Controller Interface Specification for USB (OHCI) Revision 1.0a. It provides USB host connectivity for USB low-speed (1.5M bit/sec maximum) and full-...
Page 548 This is accomplished in the OMAP5910 device by setting the line to high (with an external pullup). The slave pulls the line low to initiate a transaction. This is the case when a read happens and the slave must send the read data back to the host.
Page 549 HDQ and 1-Wire Protocols Write operation: 1) Write the command or data value to the TX write register. 2) Write 0 to the R/W bit of the control and status register to indicate a write. 3) Write 1 to the go bit of the control and status register to start the actual transmit.
Page 550 HDQ and 1-Wire Protocols 5) Software must read the interrupt status register, to determine if RX was complete or whether there was a time-out. 6) Software does a read of the RX buffer register to retrieve the read data from slave. 7) Repeat for each successive byte.
Page 551 HDQ and 1-Wire Protocols An interrupt condition indicates either a TX complete, RX complete, or time-out condition. The read of the interrupt status register clears all the interrupt condi- tions. Only one interrupt signal is sent to the microcontroller and only an overall mask bit exists for the enabling and disabling of the interrupt.
Page 552 HDQ and 1-Wire Protocols b) The time-out bit is always cleared in a read. c) The completion of the operation sets the RX complete flag in the inter- rupt status register. If interrupts are masked, no interrupt is generated. The interrupt status register is always cleared at the beginning of any read or write operation.
Page 553: Read Timing Diagram
HDQ and 1-Wire Protocols 7.15.1.2 Timing Diagrams Figure 7–65 through Figure 7–67 show the timing diagram for the read, reset, and write. In HDQ, the reset pulse only contains the initialization and not the presence pulse. The timing required for the various signals are specified in the BQ2023.
Page 554: Write State Machine #1
HDQ and 1-Wire Protocols 7.15.1.3 Write State Diagram Figure 7–68. Write State Machine #1 Reset Time out = 0 IDLE Go = 0 Rnw = 0, Go = 1 Bits sent < 8 TX complete = 0 Time out = 0 Write data TX complete = 1 TX complete...
Page 555 HDQ and 1-Wire Protocols 7.15.1.5 Status Flags The status flags are provided in the status register, which contains status flags from the transmitter, the receiver, and the presence detect logic. The presence condition detected status flag is contained in the status register. This is valid only in 1-Wire mode.
Page 556: Hdq And 1-Wire Overview
The HDQ and the 1-Wire mode are selectable in software, which must be done before any transmit and receive from the module is performed. The mode is assumed static during operation of the device. Figure 7–70. HDQ and 1-Wire Overview OMAP5910 MPU TIPB (public) BQxxxx...
Page 557: Memory Map Summary
HDQ and 1-Wire Protocols 7.15.4 Software Interface The mapping of registers to the TI peripheral bus (TIPB) address signals is shown in Table 7–144 and Table 7–145. The base address for the HDQ regis- ters is FFFB:C000. No synchronization is provided by the hardware between the register clock domain and the state machine domain.
Page 558: Registers Accessible From Tipb
HDQ and 1-Wire Protocols Table 7–145. Registers Accessible From TIPB Access Type Reset Name Value Description at Address Value TX write Read/Write 0000h 31–24 Reserved—read aliased to bits 7:0, data at 8h00 writes ignored 23–16 Reserved—read aliased to bits 7:0, writes ignored 15–8 Reserved—read aliased to bits 7:0,...
Page 559 HDQ and 1-Wire Protocols Table 7–145. Registers Accessible From TIPB (Continued) Access Type Reset Name Value Description at Address Value 31–24 Control and Reserved—read aliased to bits 7:0, at 8h08 status writes ignored register 23–16 Reserved—read aliased to bits 7:0, writes ignored 15–8 Reserved—read aliased to bits 7:0,...
Page 560: Frame Adjustment Counter
Frame Adjustment Counter 7.16 Frame Adjustment Counter The frame adjustment counter counts the number of rising edges of one signal (start of frame interrupt of the USB function) during a programmable number of rising edges of a second signal (transit frame synchronization of McBSP2). This count value can then be used by system-level software to adjust the dura- tion of the two time domains with respect to each other to reduce overflow and underflow.
Page 561: Fac Top-Level Diagram
WKUP_REQ MPU_PER_RST Reset Clock generation and management OMAP5910 7.16.2 Synchronization and Counter Control Because frame-start and frame-synchronization signals are from different time domains, the FAC module synchronizes these two signals to the system clock domain and uses the synchronized signals as the count enables. The actual counters for frame synchronization and frame start are clocked by the system clock.
Page 562: Fac Module Counters And Clock Synchronization
Frame Adjustment Counter Figure 7–72. FAC Module Counters and Clock Synchronization Frame sync Frame sync FARC counter Sync circuit Frame start Frame start Sync circuit counter System clock 7-200...
Page 563: Synchronization Circuit For Frame Synchronization And Frame Start Signals
Frame Adjustment Counter Figure 7–73. Synchronization Circuit for Frame Synchronization and Frame Start Signals Synced signal Frame sync/ DFF1 DFF2 DFF3 frame start System clock Figure 7–74 shows the actual waveforms of at the output of each flip-flop and the XOR output. Figure 7–74.
Page 564: Fac Registers
Frame Adjustment Counter 7.16.3 FAC Interrupt The FAC generates 1 interrupt, FAC_IRQ (in halt mode when the FARC value is met), connected to the MPU level 2 interrupt handler, line 0 (level-sensitive) 7.16.4 FAC Clocks and Reset The FAC works with a clock (PCLK), which is provided by the ULPD from a request generated by the USB function (DS_WAKE_REQ_ON).
Page 565: Frame Adjustment Reference Count Register (Farc)
Frame Adjustment Counter The frame-adjustment counter register (FARC) is programmed with the number of frame synchronization counts over which the frame start pulses are counted. This is a 16-bit programmable fixed reference in the range of 0-65536. A value of zero disables the count operation. Table 7–147.
Page 566: Fac Control And Configuration Register (Ctrl)
Frame Adjustment Counter The control and configuration register (CTRL) is a read/write register used to configure the module. The RUN bit is used to enable the frame-start counter. If this bit is set to 0, the frame-start counting is disabled immediately. The soft- ware can use this bit as a software reset for the FAC module by setting the RUN bit to zero.
Page 567: Dsp Private Peripherals
Chapter 8 DSP Private Peripherals This chapter describes the following DSP private peripherals and their associated memory and mapping: Timers Watchdog timer Interrupt handlers Topic Page DSP Private Peripherals ........Timers .
Page 568: Highlight Of Dsp Peripherals
DSP Private Peripherals 8.1 DSP Private Peripherals Figure 8–1 shows the OMAP5910 device with the DSP private peripherals highlighted. Figure 8–1. Highlight of DSP Peripherals DSP private Private peripherals OMAP5910 peripheral bus Timers (3) DSP public peripherals Watchdog timer TMS320C55x DSP...
Page 569: Dsp Timers
Timers 8.2 Timers Figure 8–2 shows the DSP timers in detail. Three 32-bit timers are available for general-purpose housekeeping functions. The counters/timers are configurable either in autoreload or in one-shot mode with on-the-fly read capability. Each timer generates a corresponding level 1 interrupt to the DSP when equal to zero, as shown in Table 8–1, Timer Interrupt Levels.
Page 570: Timer Interrupts Levels
Timers 8.2.1 Timer Interrupt Levels Table 8–1. Timer Interrupts Levels Timer Corresponding Level 1 Interrupt Required Sensitivity Setup INT23 Edge INT22 Edge INT8 Edge The timers are counters that receive a dedicated clock from clock generator module #2 (either CK_REF or CK_GEN2 output divided by 2). This clock can be prescaled (divided down) as controlled by the prescale clock timer value (PTV) field of the control timer register (shown in Table 8–2, PTV Divisors: 32-Bit Timers).
Page 571: Timer Characteristics
Timers 8.2.2 Timer Characteristics Table 8–3. Timer Characteristics , Clock , Timer Interrupt , Timer Interrupt Period Input Clock LOAD_TIM Period Period for PTV = 0 for PTV = 7 42.67 µs 12 MHz 83.3 ns 0001 333 ns 12 MHz 83.3 ns FFFF (max interrupt 10.92 ms...
Page 572: Timer Registers
Timers 8.2.4 Timer Registers Table 8–4 lists the timer registers. Table 8–5 through Table 8–12 describe the register bits. Table 8–4. Timer Registers Register Name Description Size (Bits) Offset Reset Value CNTL_TIMER Control timer 0x00 0x0002 LOAD_TIM_HI Load timer—high 0x02 0xFFFF LOAD_TIM_LO Load timer—low...
Page 573: Control Timer Register (Cntl_Timer)
Timers Table 8–5. Control Timer Register (CNTL_TIMER) (Continued) Reset Name Value Descriptions Value 0: Stop timer Start timer With one-shot mode selected (AR = 0), bit is automatically reset by internal logic when timer equals 0. The load timer register (LOAD_TIM) is a 32-bit register (see Table 8–6 and Table 8–7).
Page 574: Read Timer High Register (Value_Tim_Hi)
Timers Table 8–8. Read Timer High Register (VALUE_TIM_HI) Reset Name Description Value 15–0 VALUE_TIM_HI Value of timer. This is the same as READ_TIM[31:16], Undefined Table 8–9. Read Timer Low Register (VALUE_TIM_LO) Reset Name Description Value 15–0 VALUE_TIM_LO Value of timer. This is the same as READ_TIM[15:0] at the time Undefined of the last TIPB read to READ_TIM_HI.
Page 575: Dsp Timer 1 Registers
Timers Table 8–10. DSP Timer 1 Registers Size Word Reset Register Name Description (Bits) Address Value CNTL_TIMER1 Timer control register 0x2800 0x0000 LOAD_TIM1 Value that must be loaded into timer 0x2802 when timer passes through 0 READ_TIM1 Timer counter 0x2804 Table 8–11.
Page 576: Watchdog Timer Interrupt
Watchdog Timer 8.3 Watchdog Timer When powered up, the timer defaults to the watchdog timer for the DSP. This configuration requires that the user program or the OS periodically write to the count register before the counter underflows to prevent the timer from generat- ing a reset to the DSP.
Page 577: Ptv Divisors: Watchdog Timer
Watchdog Timer Table 8–14. PTV Divisors: Watchdog Timer Divisor The timer period is defined by: The value of the PTV, which is forced to 7 if the timer is in watchdog mode The value of the load register The timer interrupts period is: (PTV+1) X (LOAD_TIM + 1) x 2 where t...
Page 578: Programming The Watchdog Timer In Watchdog Mode
Watchdog Timer 8.3.1 Programming the Watchdog Timer in Watchdog Mode On power up, the watchdog timer is enabled in the watchdog mode and the value loaded into the load timer register is set to the maximum value (0xFFFF). This gives the user a duration of 16,777,216 * t to change the timer mode or write a new value (different from 0xFFFF) into the load timer register.
Page 579: Watchdog Timer Registers
Watchdog Timer 8.3.3 Watchdog Timer Registers Table 8–16 shows the DSP watchdog timer registers. Table 8–17 through Table 8–20 describe the register bits. Table 8–16. DSP Watchdog Timer Registers Reset Register Name Description Size (Bits) Address Value CNTL_TIMER Control timer x003400 0x0002 LOAD_TIM...
Page 580: Load Timer Register (Load_Tim)
Watchdog Timer Table 8–18. Load Timer Register (LOAD_TIM) Reset Name Description Value 15–0 LOAD_TIM General-purpose timer. This value is loaded when timer passes through FFFF 0 or when it starts. Watchdog timer. Reload timer with this value. Table 8–19. Read Timer Register (READ_TIM) Reset Name Description...
Page 581: Dsp Interrupt Handler Cascade
DSP core (see Table 8–21, DSP Level 1 Interrupt Mapping). The 16 level 2 interrupts are handled by the external interrupt controller, cascaded into INT3 of the DSP internal interrupt controller. Figure 8–3. DSP Interrupt Handler Cascade OMAP5910 OMAP Gigacell INTH RESET (Level-2)
Page 582: Level 1 Interrupt Mapping
Interrupt Handlers 8.4.1 Level 1 Interrupts The DSP level 1 interrupt controller receives interrupts from peripherals and sends them to the DSP core (see Table 8–21). The TI peripheral bus is respon- sible for prioritizing, capturing, and synchronizing interrupts, before sending them to the DSP.
Page 583: Level 2 Interrupts
Interrupt Handlers Table 8–21. Level 1 Interrupt Mapping (Continued) Vector Level 1 Interrupt Priority Interrupt Location IFR_bit/IMT_bit (26:0) DMA_channel_0 INT18 FFFF90 Mailbox 2 INT19 FFFF98 DMA_channel_2 INT20 FFFFA0 DMA_channel_3 INT21 FFFFA8 TIMER2 INT22 FFFFB0 TIMER1 INT23 FFFFB8 8.4.2 Level 2 Interrupts The level 2 interrupt controller provides up to 16 prioritized and maskable inter- rupts to the DSP core.
Page 584: Level 2 Interrupt Control Flow
Interrupt Handlers Figure 8–4. Level 2 Interrupt Control Flow 16 incoming interrupts Edge dectection flip_flops Edge or level direction Interrupt input register (IIR) Interrupt set register (ISR) Mask interrupt register (MIR) Interrupt level register 0 (ILR0) Process next pending IRQ Process next pending FIQ Interrupt level register 1 (ILR1) Generate IRQ...
Page 585 Interrupt Handlers 8.4.2.1 Interrupt Sequence 1) One or several incoming interrupts go down, setting the corresponding ITR bits. 2) At this time, two possibilities exist: If there is only one active incoming interrupt and FIQ is not already active, the interrupt controller sends an FIQ. When several incoming interrupts are active, the interrupt controller must determine which is the new interrupt to be serviced.
Page 586: Interrupt Handler Level 2 Registers
Interrupt Handlers Table 8–22. Interrupt Handler Level 2 Registers Default Read/ Register Name Description Value Write Size Address Interrupt 00000000 16 bits 0x004800 Interrupt mask FFFFFFFF 16 bits 0x004802 SIR_IRQ Interrupt encoded source (IRQ) 4 bits 0x004804 SIR_FIQ Interrupt encoded source (FIQ) 4 bits 0x004806 CONTROL_REG...
Page 587: Mask Interrupt Register (Mir)
Interrupt Handlers Table 8–23. Interrupt Input Register (ITR) Reset Name Type Value IRQ_15 IRQ_0 In the event of an edge-sensitive interrupt, ITR stores an incoming interrupt. When the DSP accesses the SIR_FIQ register, the bit corresponding to the interrupt that has requested the DSP action is reset. The DSP can also clear each bit individually by writing a 0 to the corresponding bits at the ITR address.
Page 588: Irq Binary-Coded Source Register (Sir_Irq)
Interrupt Handlers The mask interrupt register (MIR) operates after interrupt input register (ITR); this means that occurrences of incoming interrupts are always stored in interrupt input register (ITR). Table 8–25. IRQ Binary-Coded Source Register (SIR_IRQ) Reset Name Type Value 3–0 IRQ_NUM This register saves software processing time by recognizing the interrupt number as being either an IRQ or FIQ request.
Page 589: Interrupt Level Registers (Ilr0
Interrupt Handlers Table 8–27. Interrupt Control Register (CONTROL_REG) Reset Name Description Type Value NEW_FIQ_AGR New FIQ agreement Writing a 1 resets FIQ output and clears source FIQ register. Enables a new FIQ generation, reset by internal logic. Corresponding bit of ITR must be cleared first. NEW_IRQ_AGR New IRQ agreement Writing a 1 resets IRQ output and clears source IRQ register.
Page 590: Interrupt Level Registers (Ilr0
Interrupt Handlers Table 8–29. Interrupt Level Registers (ILR0...ILR15) Reset Name Value Description Type Value 5–2 PRIORITY Define the priority level when the corresponding interrupt is routed to IRQ or FIQ. 0 is the highest priority level. 15 is the lowest priority level. SENS_EDGE The corresponding interrupt is falling-edge-sensitive.
Page 591: Dsp Level 2 Interrupt Mapping
Interrupt Handlers 8.4.2.3 Level 2 Interrupt Mapping Table 8–30 shows the DSP level 2 interrupt mapping. Table 8–30. DSP Level 2 Interrupt Mapping Incoming Interrupts Required Sensitivity Setup Level 2 Interrupt McBSP3 TX Edge IRQ_00 McBSP3 RX Edge IRQ_01 McBSP1 TX Edge IRQ_02 McBSP1 RX...
Page 592: Dsp Interrupt Interface
DSP Interrupt Interface 8.5 DSP Interrupt Interface The DSP interrupt interface (DSP_INT_IF) augments the capability of the DSP interrupt processing by providing user-definable edge-triggered and level-sensitive implementations for each of the interrupt lines. This is neces- sary to allow edge-triggered interrupts, since the DSP level 1 interrupts must be active for greater than two DSP_CLK cycles to be recognized as being active.
Page 593: Interrupt Channel Implementation
DSP Interrupt Interface When the edge-registration flip-flop is cleared by the asynchronous reset, two DSP_INTH_CK clock periods must expire before another negative edge tran- sition can be registered. Thus successive negative transitions must be a mini- mum of six DSP_INTH_CK clock periods apart in time to be ensured of being recognized as two separate incidents.
Page 594: Level-Sensitive Interrupts
DSP Interrupt Interface 8.5.3 Level-Sensitive Interrupts The level-sensitive interrupt process is, in many ways, identical to the edge- triggered interrupt process. This process also uses a chain of four positive- edge triggered timing flip-flops, but this chain is driven by the inverted repre- sentation of the incoming interrupt nXIRQ(N).
Page 595: Edge-Triggered/Level-Sensitive Control Register Low
DSP Interrupt Interface Table 8–31. Edge-Triggered/Level-Sensitive Control Register Low Reset Name Value Description Type Value 15–0 CHx Trig/Level This bit defines whether channel CHx is edge- or level- sensitive where CHx corresponds to interrupt channels nXIRQ[15:0]. Channels nXIRQ[15:0] correspond to the DSP level 1 interrupts IRQ17:2, respectively.
Page 596: Level-Sensitive Clear Low Register (Rst_Lvl_Lo)
DSP Interrupt Interface 8.5.4.1 Level-Sensitive Clear Commands (Write Only) A write transaction issues a clear to those interrupt channels whose assigned bit in the 16-bit word being written is 1. Commands to clear interrupt channels are necessary for those channels assigned as level-sensitive interrupt chan- nels.
Page 597: Level-Sensitive Interrupt Clear Commands
DSP Interrupt Interface Table 8–34. Level-Sensitive Clear High Register (RST_LVL_HI) (Continued) Reset Name Value Description Type Value 5–0 Reset_CHx Reset CHx if a 1 is written into RST_LVL_LO[x] and CHx is configured as level-sensitive interrupt, where CHx corresponds to interrupt channels nXIRQ[20:16].
Page 598: Dsp Public Peripherals
Chapter 9 DSP Public Peripherals This chapter describes the DSP public peripherals for the OMAP5910 multimedia processor. Topic Page Introduction ..........
Page 599: Highlight Of Public Peripherals Area
Introduction 9.1 Introduction The four DSP public peripherals for the OMAP5910 processor include two multichannel buffered serial ports (McBSPs) and two multichannel serial interfaces (MCSIs): McBSP1 McBSP3 MCSI1 MSCI2 Figure 9–1 shows the OMAP5910 device with the DSP public peripherals highlighted.
Page 600: Mcbsps
Multichannel buffered serial ports (McBSPs) are configurable, high-speed, full-duplex serial ports that allow direct interface to external communications devices. There are three McBSPs on the OMAP5910 device. McBSP1 and McBSP3 are on the DSP public peripheral bus and are covered briefly in this chapter.
Page 601: Mcbsp1 Pin Descriptions
McBSP1 McBSPs / McBSP1 The operation of the OMAP5910 McBSPs is consistent with the SPRU317, with the following exceptions and clarifications: Only DXENA = 0 setting is supported. The transmit output (DX) pins don not go to high impedance when the transmitter in not actively sending data.
Page 602: Mcbsp1 Interface Diagram
McBSP1 Figure 9–2. McBSP1 Interface Diagram OMAP5910 RX (DMA_REQ_9) TX (DMA_REQ_8) RX interrupt (IRQ_3) TX interrupt (IRQ_2) DSP level 2 interrupt handler McBSP1 RX (DMA_REQ_9) TX (DMA_REQ_8) MCBSP1.CLKS System CLKS requests MCBSP1.FSX FSX_OUT FSX_OE FSX_IN MCBSP1.CLKX RX interrupt (IRQ_13) CLKX_OUT...
Page 603: Available Mcbsp1 Signals
McBSP1 The McBSP1 is half duplex, master/slave for transmission, slave for reception. Table 9–2 lists the McBSP1 signals are available at the OMAP5910 level Table 9–2. Available McBSP1 Signals Generic McBSP Signal Name Description McBSP1 Signal Name FSX2 Transmission frame (bidirectional) McBSP1.FSX...
Page 604: I2S Audio Codec Interface
McBSP1 Application Example: I2S Interface This application uses McBSP1 as an I2S audio codec interface (see Figure 9–3). The OMAP5910 is intended to be either the master or slave device; that is, it either receives or provides the frame synchronization and bit clock.
Page 605: Pin Control Register Configuration (Dsp_Write(0X0000) => Pcr)
RX frame-synchronization signal derived by external source CLKX set input pin and derived by external source CLKR set input pin and derived by external source Sample rate generator input clock mode bit the OMAP5910 CLKS pin status (no meaning in device) DX pin status...
Page 606: Receive Control Register 1 Configuration (Dsp_Write(0X00A0) => Rcr1)
McBSP1 9.3.4.3 Receive Control Register Configuration DSP_Write(0x00a0) => RCR1; set up RCR1 as shown in Table 9–6. Table 9–6. Receive Control Register 1 Configuration (DSP_Write(0x00a0) => RCR1) Config Value Description Reserved 14–8 000 0000b Set receive frame length as one word per frame 7–5 101b Set receive word length as 32 bits per frame...
Page 607: Transmit Control Register 2 Configuration (Dsp_Write(0X80A1) => Xcr2)
McBSP1 DSP_Write(0x80a1) => XCR2; set up XCR2 as shown in Table 9–9. Table 9–9. Transmit Control Register 2 Configuration (DSP_Write(0x80a1) => XCR2) Config Value Description Set dual-phase frame 14–8 000 0000b Don’t care for single-phase frame 7–5 101b Set receive word length as 32 bits per frame Set no companding data and transfer start with MSB first Set FSX not ignore after the first resets the transfer Set data delay as 1 bit...
Page 608: Waveform Example
CLK(R/X) FS(R/X) A31 A30 A29 D(R/X) 9.4 McBSP3 This section provides information specific to McBSP3 on the OMAP5910 device. For a full description of McBSP functionality and register definitions, see the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317). 9.4.1 McBSP3 Pin Descriptions Table 9–10 identifies the McBSP3 I/O pins.
Page 609: Mcbsp3 Interface Diagram
McBSP3 Figure 9–5. McBSP3 Interface Diagram OMAP5910 RX (DMA_REQ_11) TX (DMA_REQ_10) RX Interrupt (IRQ_1) TX Interrupt (IRQ_0) DSP level 2 interrupt handler McBSP3 RX (DMA_REQ_11) DSP peripheral TX (DMA_REQ_10) System fixed clock CLKS requests (12 MHz) MCBSP3.FSX FSX_OUT FSX_OE FSX_IN MCBSP3.CLKX...
Page 610: Available Mcbsp3 Signals In R = 0 Mode
The paths shown as dashed lines in Figure 9–5 are not available in this mode. Table 9–11 lists the McBSP3 signals available in this mode at the OMAP5910 level. Table 9–11. Available McBSP3 Signals in R = 0 Mode...
Page 611: Mcbsp3 Interrupt Mapping
McBSP3 9.4.2 McBSP3 Interrupt Mapping Table 9–13 identifies the McBSP3 interrupts. McBSP3 generates level 2 interrupts for both the DSP and the MPU. Table 9–13. McBSP3 Interrupt Mapping Incoming Interrupts Level 2 DSP Interrupt Level 2 MPU Interrupt McBSP3 TX interrupt IRQ_00 IRQ_10 McBSP3 RX interrupt...
Page 612: Optical Audio Interface
FSX_IN mcbsp3_clk CLKX_OUT DAU_CLK / DAU_SCLK CLKX_OE CLKX_IN Tie-off Config reg mcbsp3_dout DX_OUT DAU_DOUT / DAU_SWDT DX_OE FSR_OUT FSR_OE FSR_IN CLKR_OUT CLKR_OE CLKR_IN mcbsp3_din DR_IN DAU_DIN / DAU_SRDT Config reg DAU_DQSY (output) OMAP5910 GPIOs DAU_XLAT (input) DSP Public Peripherals 9-15...
Page 613: Serial Port Control Register Configuration (Dsp_Write(0X1000) => Spcr)
McBSP3 9.4.4.1 Serial Port Control Register Configuration DSP_Write(0x1000) => SPCR; set up SPCR1 per below configuration. Table 9–15. Serial Port Control Register Configuration (DSP_Write(0x1000) => SPCR) Config Value Description Disable digital loopback mode 14–13 Right-justify and zero-fill MSBs in DRR 12–11 Enabled clock stop mode 10–8...
Page 614: Pin Control Register Configuration (Dsp_Write(0X0A0B) => Pcr)
McBSP is set master and generate clock by internal source CLKR set input pin and derived by external source Sample rate generator input clock mode bit CLKS pin status (no meaning in OMAP5910) DX pin status DR pin status Set FSX polarity as active low...
Page 615: Receive Control Register 1 Configuration (Dsp_Write(0X0000) => Rcr1)
McBSP3 9.4.4.3 Receive Control Register Configuration The values of RWDLEN1, 2 and XWDLEN1, 2 must be set to the same value in SPI mode. DSP_Write(0x0000) => RCR1; set up RCR1 per below configuration. Table 9–17. Receive Control Register 1 Configuration (DSP_Write(0x0000) => RCR1) Config Value Description Reserved...
Page 616: Transmit Control Register 1 Configuration (Dsp_Write(0X0000) => Xcr1)
McBSP3 9.4.4.4 Transmit Control Register Configuration The values of RWDLEN1, 2 and XWDLEN1, 2 must be set to the same value in SPI mode. DSP_Write(0x0000) => XCR1; set up XCR1 per below configuration. Table 9–19. Transmit Control Register 1 Configuration (DSP_Write(0x0000) => XCR1) Config Value Description Reserved...
Page 617: Sample Rate Generator 1 Configuration (Srgr[1,2])
McBSP3 9.4.4.5 Sample Rate Generator Configuration (SRGR[1,2]) DSP_Write (0x00FF) => SRGR1; set up SRGR1 per below configuration. Table 9–21. Sample Rate Generator 1 Configuration (SRGR[1,2]) (DSP_Write (0x00FF) => SRGR1) Config Value Description 15–8 0000 0000b These bits ignored by the FSGM=0 (SRGR2[12:12]) 7–0 1111 1111b Set sample rate generator clock divider...
Page 618 McBSP3 9.4.4.7 Interrupt Flag Configuration and Clear (ILR, ITR, MIR) on Level 2 Handler 1) DSP_Write => ILR; set ILR appropriately for the interrupt handling priority. 2) DSP_Write ITR and (0xFFFF F3FF)=> ITR; clear remaining TX and RX interrupts. Note: This set up is not needed after reset.
Page 619: Waveform Example
McBSP3 9.4.4.12 Read From GPI DSP_Read <= PCR; read DR_STAT bit Figure 9–7. Waveform Example BCLKX 2 CLK BFSX A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 BDR/X Section 9.4.4.13 through Section 9.4.4.21 explain the McBSP register setup for TX master and RX slave with 8-bit data transfer using DMA support.
Page 620: Pin Control Register Configuration (Dsp_Write(0X0A0B) => Pcr)
McBSP is set master and generate clock by internal source CLKR set input pin and derived by external source Sample rate generator input clock mode bit CLKS pin status (no meaning in OMAP5910) DX pin status DR pin status Set FSX polarity as active high...
Page 621: Receive Control Register 1 Configuration (Dsp_Write(0X0000) => Rcr1)
McBSP3 9.4.4.15 Receive Control Register Configuration The values of RWDLEN1, 2 and XWDLEN1, 2 must be set to same value in SPI mode. DSP_Write(0x0000) => RCR1; set up RCR1 per below configuration. Table 9–25. Receive Control Register 1 Configuration (DSP_Write(0x0000) => RCR1) Config Value Description Reserved...
Page 622: Transmit Control Register 1 Configuration (Dsp_Write(0X0000) => Xcr1)
McBSP3 9.4.4.16 Transmit Control Register Configuration The values of RWDLEN1, 2 and XWDLEN1, 2 must be set to the same value in SPI mode. DSP_Write(0x0000) => XCR1; set up XCR1 per below configuration. Table 9–27. Transmit Control Register 1 Configuration (DSP_Write(0x0000) => XCR1) Config Value Description Reserved...
Page 623: Waveform Example
McBSP3 9.4.4.18 DMA Configuration Configure the REVT and XEVT bit for the DMA receive and transmit synchronized invent. 9.4.4.19 Interrupt Flag Configuration and Clear (ILR, MIR) 1) ARM_Write => ILR; set ILR appropriately for the interrupt handling priority. 2) ARM_Write MIR and (0x0000 0D00) => MIR; disabled SPI TX and RX interrupt Note: Enable the appropriate DMA channel interrupts.
Page 624: Multichannel Serial Interfaces
MCSIs expand the parallel interface of a DSP to connect to external devices such as codecs and GSM system simulators. The two public MCSIs on the OMAP5910 device provide full duplex transmis- sion and master or slave clock control. All transmission parameters are...
Page 625: Communication Protocol
Multichannel Serial Interfaces 9.5.1 Communication Protocol 9.5.1.1 Configuration Parameters The configuration parameters can be modified only if the MCSI is disabled (control_reg[0] = 0). Slave/Master Control Using the control bit, the interface can be configured in one of two ways: In master mode with the transmission clock and the frame synchronization pulse generated by the interface In slave mode with the transmission clock and the frame synchronization...
Page 626 Multichannel Serial Interfaces Normal/Alternate Frame Synchronization The frame-synchronization pulse position either is normal with the frame-synchronization pulse starting one bit before channel 0 or alternates with the frame-synchronization pulse starting with the first bit of channel 0. Control bit: MAIN_ PARAMETERS _REG(9) = FRAME_POSITION 1: Alternate 0: Normal Continuous/Burst Mode...
Page 627 Multichannel Serial Interfaces Word Size To choose the size of the word, set its size minus one into the main parameters registers. Control bit: MAIN_PARAMETERS_REG(3:0) = WORD_ SIZE (2 <= WORD_ SIZE <= 15) The MCSI transmits and receives the most significant bit first. For example, if the word_size equals 11, the upper 12 bits of the TX registers are transmitted, the upper 12 bits of the RX registers contain the received data, and the lower 4 bits are zeros.
Page 628: Communication Μ-Law Interface Interrupts Waveform Example
Multichannel Serial Interfaces DSP_Write(0x0007) = MAIN_PARAMETERS_REG (set up MCSI per configuration below) Bit 15-14 (00b): No DMA Bit 10 (0b): Positive polarity for frame Bit 9 (0b): Normal synchronization mode Bit 8 (0b): Short framing Bit 7 (0b): Single channel Bit 6 (0b): Slave mode Bit 5 (0b): Burst mode Bit 4 (0b): Positive edge for clock...
Page 629 Multichannel Serial Interfaces 9.5.1.3 Interface Management Interrupts Generation Three physical interrupts are available for real-time management of the MCSI by the DSP: RX_INT (data receive interrupt) TX_INT (data transmit interrupt) FERR_INT (frame duration error interrupt) RX_INT, TX_INT, and FERR_INT are maskable with dedicated programmable control bits of the interrupt register INTERRUPTS_REG.
Page 630: Receive Interrupt Timing Diagram
Multichannel Serial Interfaces Figure 9–10. Receive Interrupt Timing Diagram Channel N-1 Channel N+1 Channel N IT_RX t (syn) t (syn) t (syn) < 2 x DSPXOR_CK (12 MHz) INTERRUPT_REG(3:0) = N–1 DSP_WRITE(1) => STATUS_REG(2) Transmit Interrupt The transmit interrupt is generated every frame after the start of the transmis- sion of a data word.
Page 631: Frame Duration Error-Too Many (Long)
Multichannel Serial Interfaces Frame Duration Error Interrupt The frame duration error interrupt is only generated when: The interface is configured in burst mode (CONTINUOUS = 0). The frame duration is smaller or longer than the expected value. Namely, expected frame duration = [(channels number) * (word size)] + (over- size number) in clock periods units with over-size number defined in OVER_SIZE_REG register.
Page 632: Frame Duration Error-Too Few (Short)
Multichannel Serial Interfaces Figure 9–13. Frame Duration Error—Too Few (Short) FSYNCH received FSYNCH expected Channel 15 Channel 0 T3 T2 T7 T6 T2 T1 Over clock duration IT_FERR t (syn) t (syn) t (syn) < 2 T13 MHz DSP_WRITE(1) => STATUS_REG(0) 9.5.1.4 Interrupt Programming At module reset, RX_INT, TX_INT, and FERR_INT are masked.
Page 633: Transmit Dma Transfers
Multichannel Serial Interfaces Then, to release the interrupt signal and reset the corresponding status bits: DSP_WRITE(1) = STATUS_REG(1) for FERR_INT release STATUS_REG(2) for RX_INT release STATUS_REG(4) for TX_INT release 9.5.1.5 DMA Channel Operation Both transmit and receive operations can be supported by DMA. DMA support is enabled by control bits in the MAIN_PARAMETERS_REG: MAIN_PARAMETERS_REG(15:14) = DMA_ENABLE(1:0) TX_DMA_REQ enabled when DMA_ENABLE(0) = 1...
Page 634: Receive Dma Transfers
Multichannel Serial Interfaces Receive DMA Transfers A receive DMA transfer is initiated after the reception of the last channel of a frame, at which time all receive registers RX_REG have been updated and are ready to be read. If N channels are used, the DMA controller successively accesses all consecutive registers between RX_REG(0) and RX_REG(N-1).
Page 635 Multichannel Serial Interfaces 9.5.1.6 Interface Activation Start Sequence A typical sequence to start the interface is: 1) MCSI configuration: a) DSP_WRITE(0x0000)= CONTROL_REG in order to remove the write protection on the control registers b) DSP_WRITE(0x….)= MAIN_PARAMETERS_REG c) DSP_WRITE(0x….)= INTERRUPTS_REG d) DSP_WRITE(0x….)= CHANNEL_USED_REG e) DSP_WRITE(0x….)= CLOCK_FREQUENCY_REG DSP_WRITE(0x….)= OVER_CLOCK_REG 2) Transmit data loading for selected channels:...
Page 636: Single-Channel/Alternate Long Framing
Multichannel Serial Interfaces 9.5.1.7 Functional Mode Timing Diagrams The following timing diagrams are based on a positive clock polarity with parameter CLOCK_POL = 0. (Transmit on rising edge/receive on falling edge) Single-Channel/Alternate Long Framing Figure 9–16. Single-Channel/Alternate Long Framing FSYNCH First frame Last frame Single-Channel/Alternate Long Framing/Burst...
Page 637: Single-Channel/Alternate Short Framing/Continuous/Burst
Multichannel Serial Interfaces Single-Channel/Alternate Short Framing/Continuous/Burst Figure 9–18. Single-Channel/Alternate Short Framing/Continuous/Burst FSYNCH OVER_CLOCK_REG = 0x0003 Multichannel/Normal Short Framing/Channel4 Disable Figure 9–19. Multichannel/Normal Short Framing/Channel4 Disable FSYNCH Channel0 Channel1 Channel2 Channel3 Channel5 Channel6 Channel14 Channel15 Channel0 Multichannel/Alternate Long Framing/Continuous/Burst Figure 9–20. Multichannel/Alternate Long Framing/Continuous/Burst FSYNCH Channel0 Channel1...
Page 638: Multichannel/Normal Short Framing/Burst
Multichannel Serial Interfaces Multichannel/Normal Short Framing/Burst Figure 9–21. Multichannel/Normal Short Framing/Burst FSYNCH Channel0 Channel1 Channel14 Channel15 Channel0 Channel1 Channel2 OVER_CLOCK_REG = 0x0013 Single-Channel/Normal Short Framing Figure 9–22. Single-Channel/Normal Short Framing FSYNCH T7 T6 R4 R3 R4 R3 First frame Last frame Single-Channel/Normal Short Framing/Burst Figure 9–23.
Page 639: Single-Channel/Normal Long Framing
Multichannel Serial Interfaces OVER_CLOCK_REG = 0x0003 Single-Channel/Normal Long Framing Figure 9–24. Single-Channel/Normal Long Framing FSYNCH T7 T6 R4 R3 R4 R3 First frame Last frame Single-Channel/Normal Long Framing/Burst Figure 9–25. Single-Channel/Normal Long Framing/Burst FSYNCH T7 T6 R4 R3 R4 R3 OVER_CLOCK_REG = 0x0003 9-42...
Page 640: Single-Channel/Normal Long/Continuous
Multichannel Serial Interfaces Single-Channel/Normal Long Framing/Continuous Figure 9–26. Single-Channel/Normal Long/Continuous FSYNCH R4 R3 R4 R3 Single-Channel/Alternate Short Framing Figure 9–27. Single-Channel/Alternate Short Framing FSYNCH T7 T6 R4 R3 R4 R3 First frame Last frame Single-Channel/Alternate Short Framing/Burst Figure 9–28. Single-Channel/Alternate Short Framing/Burst FSYNCH R4 R3 R4 R3...
Page 641: Mcsi Register Descriptions
Multichannel Serial Interfaces 9.5.2 MCSI Register Descriptions Table 9–29 through Table 9–37 describe MCSI registers. CHANNEL_USED_REG, CLOCK_FREQUENCY_REG, OVER_CLOCK_REG, INTERRUPTS_REG, and MAIN_PARAMETERS_REG are write protected if the MCSI is enabled (control_reg[0] = 1). The channel selection register is only used in multichannel mode (see Table 9–29).
Page 642: Clock Frequency Register (Clock_Frequency_Reg)
Multichannel Serial Interfaces The clock frequency register is used only in master mode when the interface generates the serial clock (see Table 9–30). Table 9–30. Clock Frequency Register (CLOCK_FREQUENCY_REG) Hardware Name Description Access Reset 15–11 Unused 0000 0 10–0 clk_freq Division factor of 12-MHz reference clock 000 0000 0000 (2<=clk_freq<= 2047)
Page 643: Interrupt Masks Register (Interrupts_Reg)
Multichannel Serial Interfaces Table 9–32. Interrupt Masks Register (INTERRUPTS_REG) Hardware Name Description Access Reset 15–11 Unused 0000 0 mask_it_error Mask of frame duration error interrupt (active at 0) mask_it_tx Mask of transmit interrupt (active at 0) mask_it_rx Mask of receive interrupt (active at 0) 7–4 Number channel for it_tx Channel number for transmit interrupt...
Page 644: Main Parameters Register (Main_Parameters
Multichannel Serial Interfaces Table 9–33. Main Parameters Register (MAIN_PARAMETERS__REG) (Continued) Hardware Name Value Description Access Reset fsynch_size Frame-synchronization pulse shape Short Long Multi/single Frame structure Single Multi MCSI mode Interface transmission mode Slave Master Continuous/ Frame mode burst Burst Continuous clock_polarity Clock edge selection Positive...
Page 645: Activity Control Register (Control_Reg)
Multichannel Serial Interfaces Table 9–34. Activity Control Register (CONTROL_REG) Hardware Software Name Value Description Access Reset Reset 15–3 Reserved Reserved bits. These bits 0000 0000 0000 0000 should always be written 0000 0 0000 0 as 0. Reserved Reserved bits. These bits should always be written as 0.
Page 646: Interface Status Register (Status_Reg)
Multichannel Serial Interfaces Table 9–35. Interface Status Register (STATUS_REG) Hardware Software Name Value Description Access Reset Reset 15–7 Reserved Reserved bits. These bits 0000 0000 0 0000 0000 0 should always be written as 0. Reserved Reserved bits. These bits should always be written as 0.
Page 647: Receive Word Register (Rx_Reg[15:0])
Multichannel Serial Interfaces Table 9–36. Receive Word Register (RX_REG[15:0]) Name Access Hardware Reset Note: The MCSI receives the most significant bit first. For example, if the word_size equals 11, the upper 12 bits of the RX registers contain the received data, and the lower 4 bits are zeroes. 9-50...
Page 648: Transmit Word Register (Tx_Reg[15:0])
Multichannel Serial Interfaces Table 9–37. Transmit Word Register (TX_REG[15:0]) Name Access Hardware Reset Note: The MCSI transmits the most significant bit first. For example, if the word_size equals 11, the upper 12 bits of the TX registers are transmitted. DSP Public Peripherals 9-51...
Page 649: Mcsi1 Pin Descriptions
MCSI1 9.6 MCSI1 This section provides information specific to MCSI1 (Figure 9–29) on the OMAP5910 device. 9.6.1 MCSI1 Pin Description Table 9–38 identifies the MCSI1 I/O pins. Table 9–38. MCSI1 Pin Descriptions I/O Direction Description MCSI1.DIN Data input MCSI1.DOUT Data output MCSI1.CLK...
Page 650: Mcsi1 Interface Diagram
MCSI1 Figure 9–29. MCSI1 Interface Diagram TX (DMA_REQ_1) OMAP5910 RX (DMA_REQ_2) TX interrupt (IRQ_6) RX interrupt (IRQ_7) Frame error (IRQ_10) DSP level 2 interrupt handler MCSI1 TX (DMA_REQ_1) MCSI1.CLK RX (DMA_REQ_2) clk_out System requests Clk_out_z clk_in MCSI1.SYNC Fsynch_out Fsynch_out_z TX/RX/frame error...
Page 651: Mcsi2 Pin Descriptions
MCSI2 9.7 MCSI2 This section provides information specific to MCSI2 (Figure 9–30) on the OMAP5910 device. 9.7.1 MCSI2 Pin Description Table 9–41 identifies the MCSI2 I/O pins. Table 9–41. MCSI2 Pin Descriptions I/O Direction Description MCSI2.DIN Data input MCSI2.DOUT Data output MCSI2.CLK...
Page 652: Mcsi2 Interface Diagram
MCSI2 Figure 9–30. MCSI2 Interface Diagram TX (DMA_REQ_3) OMAP5910 RX (DMA_REQ_4) TX interrupt (IRQ_8) RX interrupt (IRQ_9) Frame error (IRQ_10) DSP level 2 interrupt handler MCSI2 MCSI2.CLK clk_out requests Clk_out_z clk_in MCSI2.SYNC Fsynch_out Fsynch_out_z TX/RX/frame error Fsynch_in interrupt (IRQ_16) Interrupts...
Page 653: Mcbsp Registers
McBSP and MCSI Memory and Peripheral Mapping 9.8 McBSP and MCSI Memory and Peripheral Mapping The base address for each McBSP register map is as follows: McBSP1 (I2S audio): 0x08C00 (DSP memory map) E101:1800 (MPU memory map) McBSP2 (modem interface): FFFB:1000 (MPU memory map) McBSP3 (optical interface): 0x0B800 (DSP memory map) E101:7000 (MPU memory map)
Page 654: Mcsi Addresses And Mapping
McBSP and MCSI Memory and Peripheral Mapping Table 9–44. McBSP Registers (Continued) Name Description Offset In Bytes XCERA(15:0) Transmit channel enable register partition A 0x20 XCERB(15:0) Transmit channel enable register partition B 0x22 PCR0(15:0) Pin control register 0x24 RCERC(15:0) Receive channel enable register partition C 0x26 RCERD(15:0) Receive channel enable register partition D...
Page 655: Mcsi Register Mapping
McBSP and MCSI Memory and Peripheral Mapping Table 9–45. MCSI Register Mapping Register Name Offset In Bytes Register Name Offset In Bytes RX15 0x7E TX10 0x54 RX14 0x7C 0x52 RX13 0x7A 0x50 RX12 0x78 0x4E RX11 0x76 0x4C RX10 0x74 0x4A 0x72 0x48...
Page 656: Mpu/Dsp Shared Peripherals
Chapter 10 MPU/DSP Shared Peripherals This chapter describes the MPU/DSP shared peripherals for the OMAP5910 multimedia processor. Topic Page 10.1 Introduction ..........
Page 657: Highlight Of Mpu/Dsp Peripherals
Introduction 10.1 Introduction The OMAP5910 device has five peripherals that appear on both MPU and DSP public peripheral buses: Mailbox registers for interprocessor communication General-purpose I/O (GPIO) UART1 UART2 UART/IrDA Figure 10–1 shows the OMAP5910 device with the MPU/DSP peripherals highlighted.
Page 658: Interprocessor Communication
Interprocessor Communication 10.2 Interprocessor Communication The MPU and DSP processors communicate with each other via a mailbox-interrupt mechanism. This mechanism provides a very flexible software protocol between the processors. The mailboxes are located in the shared memory space (byte address 0xFFFC:E000 for MPU; word address 0x0F800 for DSP).
Page 659 Interprocessor Communication instead of interrupts, the command or data registers must be polled, not the flag register. The flag registers are only useful for the interrupting processor to see if the interrupted processor has responded to the interrupt by reading the command register.
Page 660: Mailbox Registers
Interprocessor Communication Table 10–1. Mailbox Registers Byte Reset Bits Name Function Offset Value 15–0 ARM2DSP1 Writing to this location stores a software-defined data 0x00 0000 value to be used in conjunction with the ARM2DSP1 interrupt. Can be written only by the MPU. 15–0 ARM2DSP1b Writing to this location stores a software-defined...
Page 661: Interrupt Generating Mechanism
Interprocessor Communication Table 10–1. Mailbox Registers (Continued) Byte Reset Bits Name Function Offset Value 15–1 ARM2DSP1_Flag Reserved 0x18 xxxx Flag indicating that the ARM2DSP1 interrupt has been generated. Set by MPU write to ARM2DSP1b; cleared by DSP read of ARM2DSP2b. This bit can only be read by the MPU.
Page 662: General-Purpose I/O
General-Purpose I/O 10.3 General-Purpose I/O The GPIOs (see Figure 10–3) are programmable inputs or outputs. They gen- erate a level interrupt, and the sources of this interrupt can be masked from within the GPIO module. Under software control, the GPIOs can be individually dedicated to either the DSP or the MPU.
Page 663: Gpio Module Architecture
General-Purpose I/O Figure 10–3. GPIO Module Architecture DSP interrupt handler MPU_GPIO_CLKACK DSP TI MPU_GPIO_CLKREQ peripheral DSP TI DSP GPIO peripheral instance Read by DSP bus I/F GPIO Config and Control Steering control logic register MPU TI peripheral MPU TI MPU GPIO peripheral Read/write by instance...
Page 664: Data Input Register (Data_Input_Reg)
General-Purpose I/O The data input register is used to register the data that is read from the GPIO input pins. The input data is captured synchronously and clocked by an internal peripheral clock. The data input register is a read-only register. The GPIO input data is captured into this register three clock cycles after the GPIO input pin(s) change for synchronization and debouncing used to remove any input glitches.
Page 665: Interrupt Control Register (Interrupt_Control_Reg)
General-Purpose I/O The interrupt control register allows the user to define when an interrupt request occurs. The interrupt can either be generated from a high-to-low tran- sition (function 0) or a low-to-high transition (function 1). Table 10–6. Interrupt Control Register (INTERRUPT_CONTROL_REG) Access Reset Value...
Page 666: Uart1, Uart2, And Uart3/Irda
General-Purpose I/O / UART1, UART2, and UART3/IrDA UART1, UART2, and UART3/IrDA The pin control register is only in the MPU. MPU is the master and is responsi- ble for assigning the top-level GPIO I/O pins to either the MPU GPIO or the DSP GPIO.
Page 667: Lcd Controller
Chapter 11 LCD Controller This chapter describes the LCD controller module of the OMAP5910 device. Topic Page 11.1 Module Overview ..........
Page 668: Module Overview
Module Overview 11.1 Module Overview The OMAP5910 device includes an LCD controller that interfaces with most industry-standard LCD displays. The LCD controller operates only in single- panel mode (dual-panel mode is not supported). The module is designed to work with a separate RAM block to provide data to the FIFO at the front end of the LCD controller data path at a rate sufficient to support the chosen display mode and resolution.
Page 669: Lcd Controller On Board The Omap5910 Device
Module Overview Programmable pixel rate Pixel clock plus horizontal and vertical synchronization signals ac-bias drive signal Active display enable signal Figure 11–1.LCD Controller on Board the OMAP5910 Device DSP private Private peripherals OMAP5910 peripheral bus Timers (3) DSP public peripherals...
Page 670: Lcd Controller Block Diagram
Module Overview Figure 11–2.LCD Controller Block Diagram LCD controller 16-Bit TFT Frame buffer 12/16 bpp LCD.P [15:0] Palette Gray-scaler Output /serializer FIFO LCD.PCLK LCD panel LCD.VS MPU private Registers Control timings peripheral bus LCD.HS generator LCD.AC LCD_CK (from clock and reset DMA request management LCD interrupt...
Page 671 (VSYNC) signal. The pixel clock frequency is derived from the clock provided to the LCD controller (LCD_CK) from the OMAP5910 clock management logic and is programmable from LCD_CK/2 to LCD_CK/255 (see Chapter 15, Clock Generation and System Reset Management). Each time new data is supplied to the LCD data pins, the pixel clock is toggled to latch the data into the LCD display serial shifter.
Page 672: Interface To Lcd Panel Signal Descriptions
Module Overview Table 11–1. Interface to LCD Panel Signal Descriptions Name Type Destination Description LCD.P[15:0] LCD panel I/O pins used to transfer either four, eight, or sixteen data display values at a time to the LCD display. For monochrome displays, each signal represents a pixel;...
Page 673: Display Specifications
Display Specifications 11.2 Display Specifications The following information shows the number of palette entries and thus the number of possible screen colors per frame that can be displayed in each mode with the corresponding number of bits-per-pixel (BPP). Mono passive: 1 BPP, 2 BPP, 4 BPP, and 8 BPP 1 BPP: Two palette entries selecting one of 15 grayscale 2 BPP: Four palette entries selecting one of 15 grayscale 4 BPP: 16 palette entries selecting one of 15 grayscale...
Page 674 Display Specifications The vertical synchronization signal (VSYNC) width must be programmed to be as small as possible on passive screen modes, but long enough to load the palette without stealing all the memory bandwidth from the MPU. To satisfy the system requirement, the following equation must be met: ( PPL ) 1 ) 256 ) ( 15 * FDD ) ¦...
Page 675: Lcd Controller Operation
LCD Controller Operation 11.3 LCD Controller Operation The LCD controller supports a variety of user-programmable options, includ- ing display type and size, frame buffer pixel size, and output data width. Although all programmable combinations are possible, the selection of displays available within the market dictate which combinations of these programmable options are practical.
Page 676: Palette Entry/Buffer Format (8 Bpp)
LCD Controller Operation Figure 11–3.256 Palette Entry/Buffer Format (8 BPP) Individual Palette Entry † Color Red (R) Green (G) Blue (B) † Mono Unused Mono (M) † Bits-per-pixel (BPP) is only contained within the first palette entry (palette entry0). 256 Entry Palette Buffer Bit 15 Base + 0x0 Palette entry 0...
Page 677: Bits Per Pixel Encoding For Palette Entry 0 Buffer
LCD Controller Operation The first palette entry (palette entry 0) also contains an extra field that is used to configure the LCD controller synchronously at the beginning of each frame. Bits 12, 13, and 14 of the first palette entry contain a field that is used to select the number of bits-per-pixel that is to be used in the following frame and the number of entries that are used in the palette RAM.
Page 678: Bpp Frame Buffer Memory Organization
LCD Controller Operation Figure 11–5.2 BPP Frame Buffer Memory Organization Frame Buffer Byte Address Base Base + 1 Base + 2 Base + 3 • • • • • • • • • Figure 11–6.4 BPP Frame Buffer Memory Organization Frame Buffer Byte Address Base Base + 1...
Page 679: Bpp Frame Buffer Memory Organization
• • The OMAP5910 MPU operates in little endian mode and the number and posi- tion of pixels in an access depend on access type (byte, half-word, or word). For example, if the LCD controller is in 2 BPP mode and the MPU performs...
Page 680: Lookup Palette
Lookup Palette The pixel data is stored in the frame buffer the same way in all three cases (as shown in Figure 11–5); only the little endian accesses of the MPU result in the different pixel positions of each access. The top and bottom addresses of the frame buffer (palette entries + pixels data) are programmed in the DMA controller.
Page 681: Color/Grayscale Intensities And Modulation Rates
Color/Grayscale Dithering 11.5 Color/Grayscale Dithering Entries selected from the lookup palette are sent to the color/grayscale space/ timebase dither generator. Each 4-bit value is used to select one of 15 intensity levels. Two of the 16 dither values are identical (most intense). The gray/color intensity is controlled by turning individual pixels on and off at varying periodic rates.
Page 682: Output Fifo
Output FIFO 11.6 Output FIFO The LCD controller contains a 2-entry by 8-bit wide output FIFO that is used to store pixel pin data before it is driven out to the pins. Each time a modulated pixel value is output from the dither generator, it is placed into a serial shifter. The size of the shifter is controlled by programming the color/monochrome select bit in the LCD control registers.
Page 683: Lcd Controller Pins
1 depending on the inversions programmed in the timing 2 register. See Table 11–24. The OMAP5910 LCD controller provides outputs compatible with passive monochrome, passive color (STN), and active color (TFT) displays. Recom- mended connections to each type of display are outlined in the sections below.
Page 684: Passive Monochrome Panel Inputs
Each signal represents one pixel that is dithered over successive frames to achieve a maximum of 15 gray levels (see Table 11–4). Table 11–4. Passive Monochrome Panel Inputs OMAP5910 LCD Controller Output Passive Monochrome Panel Input LCD.P[0] (leftmost pixel) D[3] LCD.P[1]...
Page 685: Active Color (Tft) Panels
Connecting a 12-bit panel for 16 BPP operation involves truncating the 16 bits of data to the 12 bits required by the panel (see Table 11–6). Table 11–6. 16-Bit Per Pixel and 12-Bit Panel OMAP5910 LCD Controller Output 12-Bit TFT Panel Input LCD.P[15] (red[4]) red[3] LCD.P[14] (red[3])
Page 686: Bit Or Per Pixel And 15-Bit Panel
LCD Controller Pins Table 11–6. 16-Bit Per Pixel and 12-Bit Panel (Continued) OMAP5910 LCD Controller Output 12-Bit TFT Panel Input LCD.P[3] (blue[3]) blue[2] LCD.P[2] (blue[2]) blue[1] LCD.P[1] (blue[1]) blue[0] LCD.P[0] (blue[0]) Connecting a 15-bit panel for 16 BPP operation involves truncating the 16 bits of data to the 15 bits required by the panel (see Table 11–7).
Page 687: Bit Per Pixel And 18-Bit Panel
(see Table 11–8). Table 11–8. 16-Bit Per Pixel and 18-Bit Panel OMAP5910 LCD Controller Output 18-Bit TFT Panel Input LCD.P[15] (red[4]) red[5] LCD.P[14] (red[3])
Page 688: Bit-Per-Pixel And 24-Bit Panel
(see Table 11–9). Table 11–9. 16-Bit-Per-Pixel and 24-Bit Panel OMAP5910 LCD Controller Output 24-Bit TFT Panel Input LCD.P[15] (red[4]) red[7] LCD.P[14] (red[3])
Page 689: Lcd Controller Registers
LCD Controller Registers 11.8 LCD Controller Registers The LCD controller contains four control registers and one status register. The control registers contain bit fields to enable and disable the LCD controller to define: The height and width of the screen being controlled Color or monochrome mode Passive or active display Polarity of the control lines...
Page 690: Lcd Control Register (Lcdcontrol)
LCD Controller Registers 11.8.1 LCD Control Register 1 (LCDControl) Table 11–11. LCD Control Register (LCDControl) Reset Name Value Description Value 31–25 – Reserved 5-6-5 12 BPP (5-6-5) mode 16 bits of data are in the frame buffer, but only 12 bits are dithered and sent out.
Page 691 LCD Controller Registers Table 11–11. LCD Control Register (LCDControl) (Continued) Reset Name Value Description Value Mono 8-bit mode. Selects 4 or 8 data lines to output pixel data to the screen. LCD_PIXEL[3:0] is used to output four pixel values to the panel each pixel clock transition.
Page 692: Lcd Control Register Settings
LCD Controller Registers Table 11–12 lists suggested LCD register settings for various operating modes. Table 11–12. LCD Control Register Settings First Palette Panel Type Graphics Mode Register Setting Entry Monochrome 2 BPP 0x00400002 0x1XXX Monochrome 4 BPP 0x00400002 0x2XXX Monochrome 8 BPP 0x00010002 0x3XXX...
Page 693: Dither Logic
LCD Controller Registers The 16-bit STN mode appears in the frame buffer memory as follows: 5-6-5. Table 11–14. 16-Bit STN Data in Frame Buffer Green Blue Pins Data The 16-bit STN mode sends only 12 bits to the dither logic (bits 11, 6, 5, and 0 are not sent to dither logic).
Page 694: Tft Alternate Signal Mapping Output
LCD Controller Registers TFT Alternate Signal Mapping (TFT Map) This bit controls how the TFT pixel data are output. When this bit is set to 1, the four red bits, the four green bits, and the four blue bits are mapped to all LCD.P[15:0] output pins, as shown in Table 11–15. Table 11–15.
Page 695: Passive Mode Pixel Clock And Data Pin Timing
LCD Controller Registers LCD TFT (LCDTFT) The LCD TFT (LCDTFT) bit selects whether the LCD controller operates in passive (STN) or active (TFT) display control mode. When LCDTFT = 0: passive or STN mode is selected; all LCD data flow operates normally (including the use of the LCD dither logic);...
Page 696: Active Mode Pixel Clock And Data Pin Timing
LCD Controller Registers Figure 11–12. Active Mode Pixel Clock and Data Pin Timing LCDTFT=1 IPC=0 M8B= Don’t Care LCD.PCLK Data Pins Samples Data Pins by the Display Change Pixel 0 Pixel 1 Pixel 2 Pixel 3 LCD.P [3:0] LCD.HS LCD.VS LCD.AC 1 LCD_CK_I clock period The size of the pixel encoding is increased in TFT mode because the LCD...
Page 697: Lcd Controller Data Pin Utilization For Mono/Color, Passive/Active Panels
LCD Controller Registers Table 11–17 shows which set of LCD data pins (and LCD.P pins) is used for each mode of operation. Table 11–17. LCD Controller Data Pin Utilization for Mono/Color, Passive/Active Panels Color/Mono Passive/Active Panel Screen Portion Pins Mono 2, 4, 8 Passive Whole LCD_PIXEL[3:0]...
Page 698: Lcd Timing 0 Register (Lcdtiming0)
LCD Controller Registers 11.8.2 LCD Timing 0 Register (LcdTiming0) Table 11–18 describes the LCD timing 0 register (LcdTiming0) bits. Table 11–18. LCD Timing 0 Register (LcdTiming0) Reset Name Description Value 31–24 Horizontal back porch – Encoded value (from 1 256) used to specify number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus one).
Page 699 LCD Controller Registers Horizontal Back Porch (HBP) The 8-bit horizontal back porch (HBP) field is used to specify the number of dummy pixel clocks to insert at the beginning of each line or row of pixels. After the line clock for the previous line has been negated, the value in HBP is used to count the number of pixel clocks to wait before starting to output the first set of pixels in the next line.
Page 700: Active Mode End Of Line Timing
LCD Controller Registers Figure 11–13. Active Mode End of Line Timing HFP= HSW=0 HBP=1 LCD.PCLK LCD.HS First Data Last Data in Row LCD.P New Row LCD.AC Figure 11–14. Passive Mode End of Line Timing HFP=1 HSW=0 HBP=1 LCD.HS First pixel Last pixel data line n+1 data line n...
Page 701 LCD Controller Registers Horizontal Synchronization Pulse Width (HSW) The 6-bit horizontal synchronization pulse width (HSW) field is used to specify the pulse width of the line clock in passive mode or horizontal synchronization pulse in active mode. LCD.HS is asserted each time a line or row of pixels is output to the display and a programmable number of pixel clock delays have elapsed.
Page 702: Lcd Timing 1 Register (Lcdtiming1)
LCD Controller Registers 11.8.3 LCD Timing 1 Register (LcdTiming1) The LCD timing 1 register contains four bit fields that are used as modulus values for a collection of down counters, each of which performs a different function to control the timing of several of the LCD lines. Table 11–19 shows the location of the bit fields located in LCD timing 1 register (LCDTiming1) and provides bit descriptions.
Page 703: Active Mode End Of Frame Timing
LCD Controller Registers Vertical Back Porch (VBP) The 8-bit vertical back porch (VBP) field is used to specify the number of hori- zontal synchronizations (line clocks) to insert at the beginning of each frame. The VBP count starts just after the VSYNC signal for the previous frame has been negated for active mode or the extra horizontal synchronizations have been inserted as specified by the VSW bit field in passive mode.
Page 704: Passive Mode End Of Frame Timing
LCD Controller Registers Figure 11–16. Passive Mode End of Frame Timing VFP=1 VSW=1 VBP=2 LCD.VS LCD.HS Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î LCD.P Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Last First Second...
Page 705 LCD Controller Registers Note: The line clock transitions during the insertion of the dummy horizontal syn- chronization delay periods. VSW must be long enough to load the palette. As mentioned, VSW does not affect generation of the frame clock (i.e., vertical synchronization) signal in passive mode.
Page 706: Lcd Timing 2 Register (Lcdtiming2)
LCD Controller Registers 11.8.4 LCD Timing 2 Register (LcdTiming2) The LCD timing 2 register (LcdTiming2) contains seven different bit fields that are used to control various functions associated with the timing of the LCD controller (see Table 11–20). The LCD controller must be disabled (LCDEN = 0) when changing the state of any field within this register.
Page 707 LCD Controller Registers Table 11–20. LCD Timing 2 Register (LcdTiming2) (Continued) Reset Name Value Description Value Invert HSYNC LCD.HS pin is active high and inactive low. LCD.HS pin is active low and inactive high. Active and passive mode: horizontal synchronization pulse/line clock active between lines and after end of line wait period Invert VSYNC LCD.VS pin is active high and inactive low.
Page 708: Signal Timing When Phsvs_On_Off
LCD Controller Registers HSYNC/VSYNC Rise or Fall Programmability This bit determines whether the HSYNC/VSYNC signals are driven on the ris- ing or falling edge of the pixel clock (PHSVS_ON_OFF must be turned on first). By default, the HSYNC/VSYNC signals are driven on the falling edge of the pixel clock, and the LCD pixel data is driven on the rising edge of pixel clock.
Page 709: Signal Timing When Phsvs_On_Off
LCD Controller Registers The waveforms in Figure 11–18 show PHSVS_ON_OFF PHSVS_RISE_FALL = 0, and IPC = 1. Figure 11–18. Signal Timing When PHSVS_ON_OFF = 1 IPC=1 LCD.PCLK LCD.P[15:0] Pixel 0 HPC-1 LCD.HS VPC-1 LCD.VS LCD.AC ac-Bias Line Transactions Per Interrupt (ACBI) The 4-bit ac-bias line transitions per interrupt (ACBI) field is used to specify the number of LCD.AC line transitions to count before setting the ac-bias count status (ABC) bit in the LCD controller status register, which signals an interrupt...
Page 710 (see Table 11–21). PCD can generate a range of pixel clock frequencies from LCD_CK/2 to LCD_CK/255, where LCD_CK is the LCD controller clock from the OMAP5910 clock management logic (see Chap- ter 15, Clock Generation and System Reset Management). The pixel clock frequency must be adjusted to meet the required screen refresh rate.
Page 711: Minimum Pixel Clock Divider (Pcd)
LCD Controller Registers All of these factors alter the time duration from one frame transmission to the next. Different display manufacturers require different frame refresh rates, depending on the physical characteristics of the display. The PCD is used to alter the pixel clock frequency in order to meet these requirements. The PCD is also used in parallel data input mode to select the frequency of pixel clock.
Page 712: Lcd Status Register (Lcdstatus)
LCD Controller Registers Table 11–22. LCD Status Register (LcdStatus) Reset Name Value Description Value 31–7 – Reserved Loaded palette (read-only) The palette is not loaded. The palette is loaded. FIFO underflow status (read-only). Cleared by setting LCDEN to 0, which also resets the input FIFO in the DMA controller. FIFO has not underrun.
Page 713: Lcd Subpanel Register (Lcdsubpanel)
LCD Controller Registers Table 11–23. LCD Subpanel Register (LcdSubpanel) Reset Name Value Description Value SPEN Subpanel enable Function disabled Subpanel function mode enabled Reserved HOLS High or low signal The field indicates the position of subpanel compared to the LPPT value.
Page 714: Lcd Subpanel Display Register (Lcdsubpanel)
LCD Controller Registers Figure 11–19. LCD Subpanel Display Register (LcdSubpanel) PANEL Line N Line N Threshold Threshold Line 0 Line 0 SPEN = 1 SPEN = 1 HOLS = 0 HOLS = 1 Line N LPPT = n Line n+1 Line N Line 0 11-48...
Page 715: Lcd Panel Signals Reset Values
Interface to LCD Panel Signal Reset Values 11.9 Interface to LCD Panel Signal Reset Values The LCD panel signal outputs can accept two distinct reset values (see Table 11–24): After a hardware reset by setting the LCD_RESET_I signal to low By disabling the LCD (setting LCDEN bit to low) The default value depends solely upon the signal polarity control, as defined in the LCD timing 2 register, except for LCD.P[15:0] when driven...
Page 716: Uart Devices
Chapter 12 UART Devices This chapter describes the three universal asynchronous receiver/transmitter (UART) devices in the OMAP5910 multimedia processor. Topic Page 12.1 UART Introduction ......... . .
Page 717: Uart Modem Module
Either the MPU (default) or the DSP controls the three UARTs in the OMAP5910 processor via three TIPB switches (one for each UART). Figure 12–1 shows the OMAP5910 device with the UART modem module highlighted. UART1 and 2 are UART modems with autobaud capability.
Page 718: Main Uart Features (Uart1/2/3)
UART Introduction 12.1.1 Main UART Features (UART1/2/3) The main features are as follows: Selectable UART/autobaud modes (UART1 and 2 only) Dual 64-entry FIFOs for received and transmitted data payload Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation Programmable sleep mode Complete status reporting capabilities in both normal and sleep mode Frequency prescaler values from 0 to 65535 to generate the appropriate...
Page 719: Uart Signals
UART Introduction 12.1.1.2 IrDA Functions (UART3 Only) Slow infrared (SIR) operations Framing error, cyclic redundancy check (CRC) error, abort pattern (SIR) detection 8-entry status FIFO (with selectable trigger levels) available to monitor frame length and frame errors Table 12–1 describes the I/O module at the module level. 12.1.1.3 UART Signals The signals available on the UART modules are illustrated in Figure 12–2.
Page 720: I/O Description
UART Introduction Table 12–1. I/O Description Reset Signal Description Value UART/MODEM Signals Serial data input – Serial data output Clear to send. – Active-low modem status signal. Reading bit 4 of the modem status register checks the condition of CTS. Reading bit 0 of that register checks a change of state of CTS since the last read of the modem status register.
Page 721: Available Uart1 Signals
Each UART is controllable through a TIPB switch, either by the MPU (default) or the DSP. 12.2.1 UART1 Environment UART1 is a UART modem with autobaud capability. Table 12–2 lists the UART1 modem signals accessible at the OMAP5910 level. Table 12–2. Available UART1 Signals Generic UART Signal Name Description...
Page 722: Uart1 Environment
UART Environments Figure 12–3 shows the UART1 environment. Figure 12–3. UART1 Environment OMAP5910 ULPD 48 MHz UART1 Uart1_dpll_clk FCLK UART1.TX Input clock 12 MHz UART1.RX UART1.CTS TIPB switch P_CLK UART1.RTS NBESET P_NBRST DSP PER_CLK (12 MHz) CLKIN_DSP UART1.DTR MPU PER_CLK (12 MHz)
Page 723: Available Uart2 Signals
UART Environments 12.2.2 UART2 Environment UART2 is an UART modem with autobaud capability. Table 12–3 lists the UART2 modem signals accessible at the OMAP5910 level. Table 12–3. Available UART2 Signals Generic UART Signal Name Description UART1 Signal Name Serial data input...
Page 724: Uart2.Rx Wakeup Sequence
Putting the baud clock outside of the device enables an external UART to use this baud clock to remain synchronized even while the OMAP5910 device is in deep sleep. If the external UART sends a byte when the OMAP5910 device uis in deep sleep, it isreceived by UART2 correctly without loss of data, although at a slow rate.
Page 725: Uart2 Environment
Interrupt line IRQ[15] of the MPU level 2 interrupt handler Interrupt line IRQ[4] of the DSP level 2 interrupt handler Figure 12–5 shows the UART2 environment. Figure 12–5. UART2 Environment OMAP5910 UART2 Activity Periph_clk_nreq detection chip_nwakeup...
Page 726: Available Uart3 Signals In Irda = 1 Mode
You can use the IRDA_SELECT signal to control the multiplexing on the UART3 I/Os between the UART3 modem signals and the UART3 IrDA signals. Table 12–4 lists the UART3 IrDA signals accessible at the OMAP5910 level when IRDA_SELECT = 1.
Page 727: Uart3 Environment
UART Environments The functional clock is either a 12-MHz or a 48-MHz clock. You can select the clock with the CONF_MOD_UART3_CLK_MODE_R bit (30) of the MOD_CONF_CTRL_0 register (see Section 6.8, OMAP5910 Configuration Registers) as follows: CONF_MOD_UART3_CLK_MODE_R = 0: 12 MHz (default)
Page 728: Mpu Registers
UART Environments 12.2.4 TIPB Switch By default, the three UARTs are controllable from the MPU public TIPB. The three TIPB switch modules allow you to change the default configuration individually and thus to control the UARTs from the DSP public TIPB. This change can only be done during the boot time.
Page 729: Dsp Registers
UART Environments Table 12–8. TIPB Switch Status MPU Register (RHSW_ARM_STA) Reset Name Value Function Value 15–4 Reserved – – – RHSW_BOTH_LCK_ERR Normal operation Lock error RHSW_ITPEND_ERR Normal operation DMA request error RHSW_DMAREQ_ERR Normal operation IT pending error RHSW_ERR_NIRQ Clears IRQ line and all others status bits of register Normal operation Table 12–9.
Page 730: Tipb Switch Configuration Dsp Register (Rhsw_Dsp_Cnf)
UART Environments Table 12–10. TIPB Switch Configuration DSP Register (RHSW_DSP_CNF) Reset Name Value Function Value 15–2 Reserved – – – DSP_PERIPH_LOCK No lock DSP bus is allocated. ARM_PERIPH_LOCK No lock MPU bus is allocated. Table 12–11. TIPB Switch Status DSP Register (RHSW_DSP_STA) Reset Name Value...
Page 731: Switching Procedures
UART Environments 12.2.5 Switching Procedures The following procedures enable you to switch from MPU to DSP. For switching UART1 to DSP: 1) MPU: Write 0 into the UART1 TIPB switch configuration MPU register (RHSW_ARM_CNF) to unlock UART1. 2) DSP: Write 2 into the UART1 TIPB switch status DSP register (RHSW_DSP_CNF) to lock UART1.
Page 732: Uart Modem Register Program
UART/Autobaud Control and Status Registers 12.3 UART/Autobaud Control and Status Registers The programming combinations for register selection are shown in Table 12–12. 12.3.1 UART/Autobaud Modem Register Mapping UART1 and UART2 are accessible as follows: MPU (32-bit-byte aligned address) from the following base addresses: UART1: 0xFFFB 0000 UART2: 0xFFFB 0800 DSP (16-bit-aligned word address) from the following base addresses:...
Page 733: Uart/Autobaud Registers
UART/Autobaud Control and Status Registers Table 12–12. UART Modem Register Program (Continued) Registers LCR[7] = 1 Byte Byte Byte Byte Byte Byte LCR[7:0] ≠ 0xBF LCR[7] = 0 LCR[7:0] = 0xBF Off- Off- Off- Off- Off- Off- READ WRITE READ WRITE READ WRITE...
Page 734 UART/Autobaud Control and Status Registers Table 12–13. UART/Autobaud Registers (Continued) Register Description Size Access Modem status 8-bit Interrupt enable (IER) 8-bit Interrupt identification (IIR) 8-bit Enhanced feature 8-bit XON1 XON1 8-bit XON2 XON2 8-bit XOFF1 XOFF1 8-bit XOFF2 XOFF2 8-bit Scratchpad 8-bit Divisor latch low...
Page 735: Receive Holding Register (Rhr)
UART/Autobaud Control and Status Registers Table 12–14. Receive Holding Register (RHR) Reset Name Function Value 7–0 Receive holding register Undefined The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The THR is actually a 64-byte FIFO. The host (MPU or DSP) writes data to the THR.
Page 736 UART/Autobaud Control and Status Registers Table 12–16. FIFO Control Register (FCR) (Continued) Reset Name Value Function Value 5–4 TX_FIFO_TRIG Sets the trigger level for the TX FIFO: If SCR6 = 0 and TLR3:0 = 0000: 8 characters 16 characters 56 characters 60 characters If SCR6 = 0 and TLR3:0 ≠...
Page 737: Supplementary Control Register (Scr)
UART/Autobaud Control and Status Registers Table 12–17. Supplementary Control Register (SCR) Reset Name Value Function Value RX_TRIG_GRANU1 Disables the granularity of 1 for trigger RX level Enables the granularity of 1 for trigger RX level TX_TRIG_GRANU1 Disables the granularity of 1 for trigger TX level Enables the granularity of 1 for trigger TX level...
Page 738: Line Control Register (Lcr)
UART/Autobaud Control and Status Registers Table 12–18. Line Control Register (LCR) Reset Name Value Function Value DIV_EN Normal operating condition Divisor latch enable. Allows access to DLL, DLH, and other registers (see the register mapping). BREAK_EN Break control bit. Normal operating condition Forces the transmitter output to go low to alert the communication terminal PARITY_TYPE2...
Page 739: Uart Mode Line Status Register (Lsr)
UART/Autobaud Control and Status Registers Table 12–18. Line Control Register (LCR) (Continued) Reset Name Value Function Value 1–0 CHAR_LENGTH Specifies the word length to be transmitted or received. 5 bits 6 bits 7 bits 8 bits Note: As soon as LCR[6] is set to 1, the RX line is forced to 0 and remains in this state as long as LCR[6] = 1. Table 12–19.
Page 740 UART/Autobaud Control and Status Registers Table 12–19. UART Mode Line Status Register (LSR) (Continued) Reset Name Value Function Value RX_FE No framing error in data being read from RX FIFO Framing error occurred in data being read from RX FIFO (i.e., received data did not have a valid stop bit).
Page 741: Supplementary Status Register (Ssr)
UART/Autobaud Control and Status Registers Table 12–20. Supplementary Status Register (SSR) Reset Name Value Function Value 7–2 – Reserved 000000 RX_CTS_DSR_WAKE_ No falling edge event on RX, CTS and UP_STS A falling edge occurred on RX, CTS or DSR. TX_FIFO_FULL TX FIFO not full TX FIFO full Note:...
Page 742: Modem Status Register (Msr)
UART/Autobaud Control and Status Registers Table 12–21. Modem Control Register (MCR) (Continued) Reset Name Value Function Value RESERVED Reserved. This bit must always be written as 0: Forces RTS output to inactive (high) Forces RTS output to active (low) In loopback mode controls MSR4. If automatic RTS is enabled, the RTS output is controlled by hardware flow control.
Page 743: Uart Mode Interrupt Enable Register (Ier)
UART/Autobaud Control and Status Registers The interrupt enable register (IER) can be programmed to enable/disable any of the following interrupts: Receiver error XOFF received CTS/RTS change of state from low to high These interrupts can be enabled/disabled individually. There is also a sleep mode enable bit.
Page 744: Uart Mode Interrupt Identification Register (Iir)
UART/Autobaud Control and Status Registers The IIR is a read-only register that provides the source of the interrupt in a prioritized manner. Table 12–24. UART Mode Interrupt Identification Register (IIR) Reset Name Value Function Value 7–6 FCR_MIRROR Mirror the contents of FCR(0) on both bits 5–1 IT_TYPE Priority...
Page 745: Efr[0-3]: Software Flow Control Options
UART/Autobaud Control and Status Registers Table 12–25. Enhanced Feature Register (EFR) (Continued) Reset Name Value Function Value SPECIAL_CHAR_ Normal operation DETECT Special character detect enable Received data is compared with XOFF2 data. If a match occurs, the received data is transferred to FIFO and IIR bit 4 is set to 1 to indicate a special character has been detected.
Page 746: Xon1 Register (Xon1)
UART/Autobaud Control and Status Registers Table 12–27. XON1 Register (XON1) Reset Name Function Value 7–0 XON_WORD1 Used to store the 8-bit XON1 character 0x00 Table 12–28. XON2 Register (XON2) Reset Name Function Value 7–0 XON_WORD2 Used to store the 8-bit XON2 character 0x00 Table 12–29.
Page 747: Divisor Latch Low Register (Dll)
UART/Autobaud Control and Status Registers The divisor latch low register (DLL) and divisor latch high register (DLH) store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most significant part of the divisor; DLL stores the least significant part of the divisor.
Page 748: Transmission Control Register (Tcr)
UART/Autobaud Control and Status Registers The transmission control register (TCR) stores the receive FIFO threshold levels to start/stop transmission during hardware/software flow control. Table 12–34. Transmission Control Register (TCR) Reset Name Function Value 7–4 RX_FIFO_TRIG_START RCV FIFO trigger level to RESTORE 0000 transmission (0 –...
Page 749: Tx Fifo Trigger Level Setting Summary
UART/Autobaud Control and Status Registers Table 12–36 and Table 12–37 summarize the different ways to set the trigger levels for the transmit FIFO and the receive FIFO. Table 12–36. TX FIFO Trigger Level Setting Summary SCR[6] TLR[3:0] TX FIFO Trigger Level 0000 Defined by FCR5:4 (either 8, 16, 32, 56 spaces) 00000...
Page 750: Mode Definition Register 1 (Mdr1)
UART/Autobaud Control and Status Registers The mode of operation can be programmed by writing to MDR1[2:0]; therefore the MDR1 must be programmed on start-up after configuration of the configu- ration registers (DLL, DLH, LCR). The value of MDR1[2:0] must not be changed again during normal operation.
Page 751: Osc_12_Mhz Register Select (Osc_12M_Sel)
UART/Autobaud Control and Status Registers Table 12–39. Autobauding Status Register (UASR) (Continued) Reset Name Value Function Value 4–0 SPEED Used to report the speed identified 0000 00000 No speed identified 00001 115 200 bauds 00010 57 600 bauds 00011 38 400 bauds 00100 28 800 bauds 00101 19 200 bauds 00110...
Page 752: Module Version Register (Mvr)
UART/Autobaud Control and Status Registers / UART/Autobaud Modes of Operation UART/Autobaud Modes of Operation Table 12–41. Module Version Register (MVR) Reset Name Function Value † MAJOR_REV Major revision number of the module MINOR_REV Minor revision number of the module † For example: MVR = 0x11 => Version 1.1 12.4 UART/Autobaud Modes of Operation The UART/autobaud module can operate in two different modes: UART mode and UART with autobaud mode.
Page 753: Uart Data Format
UART/Autobaud Functional Description UART/Autobaud Modes of Operation / UART/Autobaud Functional Description 12.4.2 UART Mode With Autobauding The UART modem module is enhanced with an autobauding functionality, which in control mode allows automatically setting the speed, the number of bits per character, and the parity selected (see Figure 12–7). Figure 12–7.
Page 754: Generic Interrupt Descriptions In Modem Mode
UART/Autobaud Functional Description 12.5.2 Trigger Levels The UART provides programmable trigger levels for both receiver and trans- mitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled (in effect, the trigger level is the default value of one byte). Programmable trigger level is an enhanced feature available via the trigger level register (TLR).
Page 755 UART/Autobaud Functional Description Table 12–42. Generic Interrupt Descriptions in Modem Mode (Continued) Priority Interrupt IIR[5 - 0] Interrupt Source Interrupt Reset Method Level Type 0 1 0 0 0 0 XOFF Receive XOFF characters(s)/ Receive XON character(s), if interrupt/special special character XOFF interrupt/read of IIR, if character special character interrupt...
Page 756: Receive Fifo It Request Generation
UART/Autobaud Functional Description Figure 12–9. Receive FIFO IT Request Generation Host acknowledged IT request and transferred enough bytes to recover FIFO level below Receive FIFO Level threshold Programmable flow control threshold Programmable FIFO threshold Zero byte time Interrupt request Interrupt request active low time In receive, no interrupt is generated until receive FIFO reaches its threshold.
Page 757: Fifo Polled Mode
UART/Autobaud Functional Description 12.5.4 FIFO Polled Mode In FIFO polled mode (FCR [0] = 0, relevant interrupts disabled via IER) the status of the receiver and transmitter can be checked by polling the line status register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the host (MPU or DSP).
Page 758: Receive Fifo Dma Request Generation
UART/Autobaud Functional Description 12.5.5.2 DMA Transfers Figure 12–11 shows DMA operation at receive; Figure 12–12 shows DMA operation at transmit. Figure 12–11. Receive FIFO DMA Request Generation Receive FIFO level Programmable threshold Zero byte time DMA request DMA request active low time Threshold reads From system DMA...
Page 759: Sleep Mode
UART/Autobaud Functional Description In transmit mode, a DMA request is automatically asserted when FIFO is empty. This request is deasserted when the number of bytes defined by the threshold level has been written by the system DMA. The DMA request is again asserted if the FIFO is able to receive the number of bytes defined by the threshold.
Page 760: Break And Time-Out Conditions
UART/Autobaud Functional Description 12.5.7 Break and Time-out Conditions Time-out counter The RX idle condition is detected when the RX line has been high for a time equivalent to (4X programmed word length) plus12 bits. The receiver line is sampled midway through each bit. For sleep mode, the counter is reset when there is activity on the RX line.
Page 761: Hardware Flow Control
UART/Autobaud Functional Description 12.5.9 Hardware Flow Control Hardware flow control is composed of automatic RTS and automatic CTS. Both can be enabled/disabled independently by programming EFR[7:6]. With automatic CTS, CTS must be active before the module can transmit data. Automatic RTS only activates the RTS output when there is enough room in the FIFO to receive data, and it deactivates the RTS output when the RX FIFO is sufficiently full.
Page 762: Software Flow Control
UART/Autobaud Functional Description 12.5.10 Software Flow Control Software flow control is enabled through the enhanced feature register (EFR) and the modem control register (MCR). Different combinations of software flow control can be enabled by setting different combinations of EFR[3 - 0]. There are two other enhanced features related to software flow control: XON any function [MCR(5)]: Operation resumes after receiving any character after recognizing the XOFF character.
Page 763: Autobauding Mode
UART/Autobaud Functional Description 12.5.10.2 TX With XOFF1, two characters are transmitted when the RX FIFO has passed the programmed trigger level TCR(3:0). With XON1, two characters are transmitted when the RX FIFO reaches the trigger level programmed via TCR(7:4). After an XOFF character has been sent, if software flow control is disabled, the module transmits XON characters automatically to enable normal transmis- sion to proceed.
Page 764 UART/Autobaud Functional Description The following settings are allowed in autobaud mode: Speed: 115.2K baud, 57.6K baud, 38.4K baud, 28.8K baud, 19.2K baud, 14.4K baud, 9.6K baud, 4.8K baud, 2.4K baud, or 1.2K baud. Length: 7 or 8 bits Parity: Odd, even, or space Combination 7-bit space parity is forbidden.
Page 765: Autobaud State Machine
UART/Autobaud Configuration Example UART/Autobaud Functional Description / UART/Autobaud Configuration Example Figure 12–13. Autobaud State Machine !(A a) Wait a or A <CR> !(A a t) no PE !(A a T) Wait T Wait t (Baud rate (Baud rate acquired) acquired) Reception !<CR>...
Page 766: Uart Sw Reset
UART/Autobaud Configuration Example 12.6.1 UART SW Reset he goal is to clear IER and MCR registers, remove UART breaks (LCR[6] = 0), and put the module in reset (MDR1[2:0] = 0x3). 1) To write into both the IER and MCR registers, set EFR[4] to 1. 2) To enable access to the EFR register, write 0xBF to the LCR register: LCR = 0xBF EFR[4] = 1...
Page 767: Uart Irda Register Program
UART/IrDA Control and Status Registers 12.7 UART/IrDA Control and Status Registers Each register is selected using a combination of address and some LCR register bit settings, as shown in Table 12–43. UART3 is accessible as follows: MPU (32-bit aligned byte address) from the following base address: UART3: 0xFFFB 9800 DSP (16-bit aligned word address) from the following base address: UART3: 0x00CC00...
Page 768: Uart/Irda Registers
UART/IrDA Control and Status Registers Table 12–43. UART IrDA Register Program (Continued) Registers LCR[7] = 1 Byte Byte Byte Byte Byte Byte LCR[7:0] ≠ 0xBF LCR[7] = 0 LCR[7:0] = 0xBF Off- Off- Off- Off- Off- Off- READ WRITE READ WRITE READ WRITE...
Page 769 UART/IrDA Control and Status Registers Table 12–44. UART/IrDA Registers (Continued) Register Description Access Interrupt identification (IIR) 8 bits R Enhanced feature 8 bits R/W XON1/ADDR1 XON1/Address 1 8 bits R/W XON2/ADDR2 XON2/Address 2 8 bits R/W XOFF1 XOFF1 8 bits R/W XOFF2 XOFF2 8 bits R/W...
Page 770: Receive Holding Register (Rhr)
UART/IrDA Control and Status Registers The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the RHR.
Page 771: Fifo Control (Fcr) Register
UART/IrDA Control and Status Registers Table 12–47. FIFO Control (FCR) Register Reset Name Value Function Value 7–6 RX_FIFO_TRIG Sets the trigger level for the RX FIFO: If SCR7 = 0 and TLR7:4 = 0000: 8 characters 16 characters 56 characters 60 characters If SCR7 = 0 and TLR7:4 0 0000, RX_FIFO_TRIG is not considered.
Page 772 UART/IrDA Control and Status Registers Table 12–47. FIFO Control (FCR) Register (Continued) Reset Name Value Function Value DMA_MODE DMA_MODE 0 (no DMA) DMA_MODE 1 (UART_nDMA_REQ0 in TX, UART_nDMA_REQ1 in RX) This register is considered if SCR0 = 0. TX_FIFO_CLEAR No change Clears the transmit FIFO and resets its counter logic to zero.
Page 773: Supplementary Control Register (Scr)
UART/IrDA Control and Status Registers Table 12–48. Supplementary Control Register (SCR) Reset Name Value Function Value RX_TRIG_GRANU1 Disables the granularity of 1 for trigger RX level Enables the granularity of 1 for trigger RX level TX_TRIG_GRANU1 Disables the granularity of 1 for trigger TX level Enables the granularity of 1 for trigger TX level...
Page 774 UART/IrDA Control and Status Registers The line control register (LCR) [6:0] defines parameters of the transmission and reception. Table 12–49. Line Control Register (LCR) Reset Name Value Function Value DIV_EN Normal operating condition Divisor latch enable. Allows access to DLL, DLH, and other registers (refer to the registers mapping).
Page 775: Uart Mode Line Status Register (Uart_Lsr)
UART/IrDA Control and Status Registers Table 12–49. Line Control Register (LCR) (Continued) Reset Name Value Function Value CHAR_LENGTH Specify the word length to be transmitted or received. 5 bits 6 bits 7 bits 8 bits Note: As soon as LCR[6] is set to 1, the RX line is forced to 0 and remains in this state as long as LCR[6] = 1. Table 12–50.
Page 776 UART/IrDA Control and Status Registers Table 12–50. UART Mode Line Status Register (UART_LSR) (Continued) Reset Name Value Function Value RX_FE No framing error in data being read from RX FIFO Framing error occurred in data being read from RX FIFO (received data did not have a valid stop bit).
Page 777: Sir Mode Line Status Register (Sir_Lsr)
UART/IrDA Control and Status Registers Table 12–51. SIR Mode Line Status Register (SIR_LSR) Reset Name Value Function Value THR_EMPTY Transmit hold register is not empty. Transmit hold register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is enabled.
Page 778: Supplementary Status Register (Ssr)
UART/IrDA Control and Status Registers Table 12–51. SIR Mode Line Status Register (SIR_LSR) (Continued) Reset Name Value Function Value RX_FIFO_E At least one data character in the RX_FIFO No data in the receive FIFO When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read).
Page 779 UART/IrDA Control and Status Registers The modem control register (MCR) [3:0] controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 12–53. Modem Control Register (MCR) Reset Name Value Function Value CLKSEL No action Divide clock input by 4.
Page 780: Modem Status Register (Msr)
UART/IrDA Control and Status Registers The modem status register (MSR) provides information about the current state of the control lines from the modem, data set, or peripheral device to the host (MPU or DSP). It also indicates when a control input from the modem changes state.
Page 781 UART/IrDA Control and Status Registers The interrupt enable register (IER) in UART mode can be programmed to enable/disable any of the following interrupts: Receiver error XOFF CTS/RTS change of state from low to high Each of these interrupts can be enabled/disabled individually. There is also a sleep mode enable bit.
Page 782 UART/IrDA Control and Status Registers The interrupt enable register (IER) in SIR mode can be programmed to enable/ disable any of the following interrupts: Received error TX underrun Status FIFO RX overrun Last byte in RX FIFO Each of these interrupts can be enabled/disabled individually. There is also a sleep mode enable bit.
Page 783 UART/IrDA Control and Status Registers The interrupt identification register (IIR) is a read-only register, which provides the source of the interrupt in a prioritized manner. Table 12–57. UART Mode Interrupt Identification Register (UART_IIR) Reset Name Value Function Value 7–6 FCR_MIRROR Mirror the contents of FCR(0) on both bits.
Page 784 UART/IrDA Control and Status Registers The IRQ output is activated whenever one of the 8 interrupts is active. Table 12–58. SIR Mode Interrupt Identification Register (SIR_IIR) Reset Name Value Function Value EOF_IT Received EOF interrupt inactive Received EOF interrupt active LINE_STS_IT Receiver line status interrupt inactive Receiver line status interrupt active...
Page 785 UART/IrDA Control and Status Registers The enhanced feature register (EFR) enables or disables enhanced features, most of which only apply to UART mode. But EFR[4] enables write accesses to FCR[5:4], the TX trigger level, which is also used in SIR mode. Table 12–59.
Page 786: Efr[0:3]: Software Flow Control Options
UART/IrDA Control and Status Registers Table 12–60. EFR[0:3]: Software Flow Control Options Bit 3 Bit 2 Bit 1 Bit 0 TX, RX Software Flow Controls No transmit flow control Transmit XON1, XOFF1 Transmit XON2, XOFF2 † Transmit XON1, XON2: XOFF1, XOFF2 No receive flow control Receiver compares XON1, XOFF1 Receiver compares XON2, XOFF2...
Page 787: Xoff2 Register (Xoff2)
UART/IrDA Control and Status Registers Table 12–64. XOFF2 Register (XOFF2) Reset Name Function Value 7–0 XOFF_WORD2 Used to store the 8-bit XOFF2 character in used 0x00 in UART mode. The scratchpad register (SPR) does not control the module in anyway. It is a scratchpad register to be used by the programmer to hold temporary data.
Page 788: Transmission Control Register (Tcr)
UART/IrDA Control and Status Registers The input frequency of the UART IrDA must be fixed to the operating frequency (here 12 MHz; no CLKSEL bit setting), and the the OSC_12M_SEL bit must be set to be able to reach the desired baud rate. Setting OSC_12M_SEL to 1 enables turning on the 6.5 division factor.
Page 789: Transmit Fifo Trigger Level Setting Summary
UART/IrDA Control and Status Registers Table 12–70 and Table 12–71 summarize the different ways that can be used to set the trigger levels for the transmit FIFO and the receive FIFO, respectively. Table 12–70. Transmit FIFO Trigger Level Setting Summary SCR[6] TLR[3:0] TX FIFO Trigger Level...
Page 790: Mode Definition 1 Register (Mdr1)
UART/IrDA Control and Status Registers The mode of operation can be programmed by writing to MDR1[2:0]; therefore the mode definition 1 register (MDR1) must be programmed on start-up after configuration of the configuration registers (DLL, DLH, LCR…). The value of MDR1[2:0] must not be changed again during normal operation.
Page 791: Mode Definition Register 2 (Mdr2)
UART/IrDA Control and Status Registers The mode definition 2 register (MDR2) sets the trigger level for the frame status FIFO (8 entries) and must be programmed before the mode is programmed in MDR1[2:0]. Table 12–73. Mode Definition Register 2 (MDR2) Reset Name Value...
Page 792: Received Frame Length Low Register (Rxfll)
UART/IrDA Control and Status Registers The received frame length registers (RXFLL and RXFLH) hold the 12-bit receive maximum frame length. RXFLL holds the least significant bits, and RXFLH holds the most significant bits. If the intended maximum receive frame length is n bytes, then program RXFLL and RXFLH to n + 3 in SIR mode (+3 is due to frame format with CRC and stop flag).
Page 793: Status Fifo Line Status Register (Sflsr)
UART/IrDA Control and Status Registers The status FIFO line status line register (SFLSR) reads frame status informa- tion from the status FIFO (this register does not physically exist). Reading this register increments the status FIFO read pointer (SFREGL and SFREGH must be read first).
Page 794: Status Fifo Register Low (Sfregl)
UART/IrDA Control and Status Registers The frame lengths of received frames are written into the status FIFO. This information can be read by reading the status FIFO registers (SFREGL and SFREGH—these registers do not physically exist). The least significant bits are read from SFREGL, and the most significant bits are read from SFREGH.
Page 795: Bof Length Register (Eblr)
UART/IrDA Control and Status Registers The beginning of frame length register (EBLR) specifies the number of BOF + XBOFs to transmit in IrDA SIR operations. Value set into this register must take into account the BOF character; to send sent one BOF with no XBOF, this register must be set to 1.
Page 796: Auxiliary Control Register (Acreg)
UART/IrDA Control and Status Registers With an input frequency of 12 MHz: At 115200 bauds DLH = 0x00 DLL = 0x01 MDR24:3 = 0x00 DIV_1.6 = 0x01 At 57600 bauds DLH = 0x00 DLL = 0x02 MDR24:3 = 0x00 DIV_1.6 = 0x14 At 38400 bauds DLH = 0x00 DLL = 0x03...
Page 797: Osc 12-Mhz Select Register (Osc_12M_Sel)
UART/IrDA Control and Status Registers Table 12–85. Auxiliary Control Register (ACREG) (Continued) Reset Name Value Function Value ABORT_EN Frame abort. The host can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame.
Page 798: Uart/Irda Modes Of Operation
UART/IrDA Modes of Operation 12.8 UART/IrDA Modes of Operation The UART/IrDA module can operate in two different modes: UART mode and slow infrared (SIR) mode. The modules perform serial-to-parallel conversion on data characters received and parallel-to-serial conversion on data characters transmitted by the processor.
Page 799: Irda Frame Format
UART/IrDA Modes of Operation SIR transparency is carried out if the outgoing data (between the start and stop flags) contains C0h, C1h, or 7Dh. If one of these is about to be transmitted, then the SIR state machine sends an escape character [7Dh] first, then inverts the fifth bit of the real data to be sent, and sends this data immediately after the 7Dh character.
Page 800 UART/IrDA Modes of Operation 12.8.2.2 Asynchronous Transparency Before transmitting a byte, the UART IrDA controller examines each byte in the payload and the CRC field (between BOF and EOF). For each byte equal to 0xC0 (BOF), 0xC1 (EOF), 0x7D (control escape), the controller does the following.
Page 801: Irda Encoder Mechanism
UART/IrDA Modes of Operation 12.8.2.4 Pulse Shaping In SIR mode both the 3/16 or the 1.6-µs pulse duration methods are supported. ACREG[7] selects the pulse-width method in transmit mode. 12.8.2.5 Encoder Serial data from the transmit state machine is encoded to transmit data to the optoelectronics (see Figure 12–15).
Page 802: Irda Decoder Mechanism
UART/IrDA Modes of Operation 12.8.2.6 Decoder After reset, RXD is high and the 4-bit counter is cleared (see Figure 12–16). When a rising edge is detected on RXIR, RXD falls on the next rising edge of 16XCLK with sufficient setup time. RXD remains low for 16 cycles (16XCLK) and then returns to high as required by the IrDA specification.
Page 803: Functional Block Diagram
UART/IrDA Functional Description 12.9 UART/IrDA Functional Description This section provides a functional description of the UART IrDA. 12.9.1 UART/IrDA Functional Block Diagram Figure 12–17 shows the UART/IrDA (FSM stands for finite state machine). Figure 12–17. Functional Block Diagram UART TX FSM TX FIFO TXIR TX FSM...
Page 804: Generic Interrupt Functions In Modem Mode
UART/IrDA Functional Description 12.9.3 Interrupts The UART generates interrupts on the UART_nIRQ output pin. All interrupts can be enabled/disabled by writing to the appropriate bit in the interrupt enable register (IER). The interrupt status of the device can be checked at any time by reading the interrupt identification register (IIR).
Page 805: Generic Interrupt Functions In Sir Mode
UART/IrDA Functional Description The RX_FIFO_STS bit (LSR[7]) generates the interrupt for the receiver line status interrupt. For the XOFF interrupt, if a XOFF flow character detection causes the inter- rupt, the interrupt is cleared by a XON flow character detection. If special char- acter detection causes the interrupt, the interrupt is cleared by a read of the IIR.
Page 806: Fifo Interrupt Mode
UART/IrDA Functional Description 12.9.3.3 Wake-Up Interrupt Wake-up interrupt is a uniquely designed interrupt, enabled when SCR[4] is set to 1. The IIR register is not modified when it occurs; SSR[1] must be checked to detect a wake-up event. When a wake-up interrupt occurs, the only way to clear it is to reset SCR[4] to 0.
Page 807: Fifo Polled Mode Operation
UART/IrDA Functional Description Figure 12–19. Transmit FIFO IT Request Generation Transmit FIFO level Full level Number spaces Programmable FIFO threshold Zero byte time Interrupt request Interrupt request Active low time In transmit mode, an interrupt request is automatically asserted when FIFO is empty.
Page 808: Fifo Dma Mode Operation
UART/IrDA Functional Description 12.9.6 FIFO DMA Mode Operation 12.9.6.1 DMA Signaling There are four modes of DMA operation: DMA mode 0, DMA mode 1, DMA mode 2, and DMA mode 3. They can be selected as follows. When SCR[0] = 0: Setting FCR[3] to 0 enables DMA mode 0.
Page 809: Transmit Fifo Dma Request Generation
UART/IrDA Functional Description In receive mode, a DMA request is generated as soon as the receive FIFO reaches its threshold. This request is deasserted when the number of bytes defined by the threshold level has been read by the system DMA. Figure 12–21.
Page 810: Sleep Mode
UART/IrDA Functional Description 12.9.7 Sleep Mode 12.9.7.1 UART Mode Sleep mode is a low-power, enhanced feature of the UART that can be enabled by writing a 1 to IER[4] (when EFR[4] = 1). Sleep mode is entered when: Serial RX data input line is idle. TX FIFO and TX shift register are empty.
Page 811: Break And Time-Out Conditions
UART/IrDA Functional Description 12.9.8 Break and Time-Out Conditions time-out counter An RX idle condition is detected when the receiver line, RX, has been high for a time equivalent to 4 X programmed word length + 12 bits. The receiv- er line is sampled midway through each bit. For sleep mode, the counter is reset when there is activity on the RX line.
Page 812: Hardware Flow Control
UART/IrDA Functional Description 12.9.10 Hardware Flow Control Hardware flow control is composed of automatic CTS and automatic RTS. Automatic CTS and automatic RTS can be enabled/disabled independently by programming EFR[7:6]. With automatic CTS, CTS must be active before the module can transmit data. Automatic RTS only activates the RTS output when there is enough room in the FIFO to receive data and deactivates the RTS output when the RX FIFO is sufficiently full.
Page 813: Software Flow Control
UART/IrDA Functional Description 12.9.11 Software Flow Control Software flow control is enabled through the enhanced feature register (EFR) and the modem control register (MCR). Different combinations of software flow control can be enabled by setting different combinations of EFR[3-0]. There are two other enhanced features relating to software flow control: XON Any function [MCR(5)]: Operation resumes after receiving any char- acter after recognizing the XOFF character.
Page 814: Frame Closing
UART/IrDA Functional Description 12.9.11.2 TX XOFF1: Two characters are transmitted when the RX FIFO has passed the programmed trigger level TCR(3:0). XON1: Two characters are transmitted when the RX FIFO reaches the trigger level programmed via TCR(7:4). If, after an XOFF character has been sent, software flow control is disabled, the module transmits XON characters automatically to enable normal trans- mission to proceed.
Page 815: Store And Controlled Transmission
UART/IrDA Functional Description 12.9.13 Store and Controlled Transmission In a store and controlled transmission (SCT), the host (MPU or DSP) first starts writing data into the TX FIFO. Then, after it writes a part of a frame (for a bigger frame) or a whole frame (a small frame, that is, supervisory frame), it writes a 1 to ACREG[2] (deferred TX start) to start transmission.
Page 816: Uart/Irda Configuration Example
UART/IrDA Functional Description / UART/IrDA Configuration Example / UART Software Reset UART/IrDA Configuration Example The host (MPU or DSP) uses the frame-length information to locate the frame- boundary in the received frame data. The host can screen bad frames using the error-status information and later request the sender to resend only the bad frames.
Page 817: Uart Fifo Configuration
UART FIFO Configuration 12.12 UART FIFO Configuration The goal of the UART FIFO configuration is to set trigger level for halt/restore (TCR register), set trigger level for transmit/receive (TLR register), and configure the FIFO (FCR register). The procedure of the UART FIFO configuration is as follows: 1) Write into both the TLR and TCR registers Set EFR[4] to 1 Set MCR[6] to 1.
Page 818: Usb Function Module
Chapter 13 USB Function Module This chapter describes the components and features of the OMAP5910 universal serial bus (USB) function module. Topic Page 13.1 Overview ........... .
Page 819: Overview
Standard is assumed. All references to local host (LH) in this chapter refer to the MPU processor. Figure 13–1 shows the OMAP5910 device with the USB function module high- lighted. Figure 13–2 shows the connection of the USB function module within the OMAP5910 in more detail.
Page 820: Usb Function Module
This count value can then be used by system software to adjust the duration of the two time domains with respect to each other to reduce the overflow and underflow. Figure 13–1. USB Function Module DSP private Private peripherals OMAP5910 peripheral bus Timers (3) DSP public peripherals Watchdog timer TMS320C55x DSP...
Page 821: Usb Function Environment
Overview Figure 13–2. USB Function Environment OMAP5910 OMAP5910 USB Function configuration VBUS_MODE SYSTEM DMA FUNC_MUX_CTRL_0(18) DMA_RX_REQ_ON [2:0] DMA_REQ[27:25] VBUS_CTRL FUNC_MUX_CTRL_0(19) DMA_TX_REQ_ON [2:0] MOD_CONF_CTRL_0(17) USB _GPIO DMA_REQ[30:28] FUNC_MUX_CTRL_7(11:9) MOD_CONF_CTRL_0(6:1) IRQ_GENI_ON MPU interrupt handler Irq20 level2 FUNC_MUX_CTRL_D(5:3) IRQ_NON_ISO_ON Irq30 IRQ_ISO_ON GPIO(0) Irq24...
Page 822: 13.1.3 Usb Function Clocks And Reset
Overview 13.1.3 USB Function Clocks and Reset The USB function has two clocks: An interface clock (CLOCK_I), used between the MPU TIPB and the USB function and connected to the MPU peripheral programmable clock (PERCLK), is derived by dividing CK_GEN1 (the output of DPLL1) by the value associated with the PERDIV field of the ARM_CKCTL register (0xFFFECE00).
Page 823: 13.1.5 Usb Detection
Overview 13.1.5 USB Detection When OMAP5910 is in deep sleep mode, the USB function can detect a bus connection to an external USB host or hub and generate a deep sleep wake request (DS_WAKE_REQ_ON) to wake up the system and to get the interface clock (CLOCK_I).
Page 824 Overview 13.1.5.2 Hardware Detection This detection can have two sources: The GPIO(0) OMAP5910 input The OMAP5910 input of the USB function I/O power supply (DVDD2) selection between these sources made USB_W2FC_VBUS_MODE bit(17) of the MOD_CONF_CTRL_0 register (bit usable only in OMAP5910 configuration mode): USB_W2FC_VBUS_MODE = 0 (default): GPIO(0) is selected.
Page 825: 13.1.6 Software Disconnect
Thus: PullUp_En bit=0 (by default): The external 1.5-kΩ is seen as a pulldown on the USB D+; the external USB host cannot detect the OMAP5910 USB function. PullUp_En bit=1: The external 1.5-kΩ is seen as a pullup on the USB D+, the USB host detects this level and, therefore, the presence of the OMAP5910 USB function.
Page 826: Register Map
Register Map 13.2 Register Map Table 13–1 lists the USB function registers. Table 13–2 through Table 13–24 describe the register bits. The MPU base address is FFFB:4000. Table 13–1. USB Function Module Registers Offset Register Description Access Address Revision 0x00 Endpoint EP_NUM Endpoint selection...
Page 827 Register Map Table 13–1. USB Function Module Registers (Continued) Offset Register Description Access Address DMA Configuration (Continued) TXDMA1 Transmit DMA control 1 0x54 TXDMA2 Transmit DMA control 2 0x58 Reserved 0x5C RXDMA0 Receive DMA control 0 0x60 RXDMA1 Receive DMA control 1 0x64 RXDMA2 Receive DMA control 2...
Page 828: Revision Register (Rev)
Register Map 13.2.1 Revision Register (REV) The read-only revision register (REV) contains the revision number of the module. A write to this register is forbidden. Table 13–2. Revision Register (REV) Name Description 15–8 – Reserved 7–0 Rev_nb Revision number 13.2.1.1 REV_NB This 8-bits field indicates the revision number of the current USB function module.
Page 829 Register Map 13.2.2.1 Setup FIFO Select (Setup_Sel) Set by the local host in response to a setup general USB interrupt in order to access the EP0 read-only setup FIFO when reading the DATA register. Setting this bit clears the Setup interrupt bit. When this bit is set, other EP_NUM register bits must be 0.
Page 830: Data Register (Data)
Register Map 13.2.2.3 Endpoint Direction (EP_Dir) This bit gives the direction associated with the endpoint number selected in EP_Num. 0: OUT endpoint 1: IN endpoint Value after local host or USB reset is low. 13.2.2.4 Endpoint Number (EP_Num) The endpoint number binary encoded in these four bits, associated to the direction given by EP_Dir bit, is the current endpoint selected.
Page 831: Control Register (Ctrl)
Register Map Note: Writing the DATA register when EP_Dir = 0 and reading from DATA register when EP_Dir = 1 are denied. 13.2.4 Control Register (CTRL) This set-only control register (CTRL) controls the FIFO and status of the selected endpoint. A read access to this register always returns 0. Note: The endpoint 0 setup FIFO is always enabled and ready to accept setup data.
Page 832 Register Map 13.2.4.2 Set Halt Endpoint (Set_Halt) Only concerns non-isochronous endpoints. Used by the local host to halt the selected endpoint. The halted endpoint returns STALL handshakes to the USB host. The local host can disable the endpoint interrupt if it does not wish to be informed of STALL handshakes. If the endpoint to halt is used by a DMA channel, the local host must disable the DMA channel before setting the halt conditions for this endpoint.
Page 833 Register Map The local host must never enable endpoint 0 FIFO if not performing a control transfer. For bulk and interrupt endpoints, the FIFO must never be enabled when Set_Halt = 1 (halt feature enabled) or when RX FIFO is not empty. Furthermore, during endpoint interrupt handling, the local host must have cleared the interrupt bit before setting the Set_FIFO_En bit (to avoid masked ACK interrupts).
Page 834: Status Register (Stat_Flg)
Register Map 13.2.5 Status Register (STAT_FLG) The read-only status flag register provides a status of the FIFO and the results of the transaction handshakes for the selected endpoint. The eight MSB are reserved for isochronous endpoints, while the eight LSB are reserved for non- isochronous endpoints.
Page 835 Register Map Table 13–6. Status Register (STAT_FLG) (Continued) Name Description Transaction acknowledge (non-isochronous) FIFO_En FIFO enable status (non-isochronous) Non_ISO_FIFO_Empty Non-isochronous FIFO empty Non_ISO_FIFO_Full Non-isochronous FIFO full 13.2.5.1 Isochronous Missed IN Token (Miss_In) Only concerns isochronous IN endpoints. Notifies the local host that the core missed a valid isochronous IN token during previous frame and that TX data was flushed from the FIFO instead of being transmitted to the USB host.
Page 836 Register Map This bit is updated every frame. 0: Not significant 1: Isochronous packet received with errors Value after local host or USB reset is low. 13.2.5.4 Isochronous FIFO Empty (ISO_FIFO_Empty) Only concerns isochronous endpoints. Set when the FIFO for the selected isochronous endpoint is empty, either via an appropriate write to the Clr_EP bit or the Reset_EP bit, or after successful reads from the selected FIFO.
Page 837 Register Map 13.2.5.7 Transaction Stall (STALL) Only concerns non-isochronous endpoints. This status bit is set at the end of a transaction if a STALL handshake packet was returned to the USB host, and if no interrupt is pending on current buffer. The core automatically returns a STALL packet if a valid IN token is received by a halted TX endpoint, if a valid OUT transaction is received by an halted RX endpoint, or if there is a request error (endpoint 0).
Page 838 Register Map 13.2.5.10 FIFO Enable (FIFO_En) Only concerns non-isochronous endpoints. This bit is asserted when the Set_FIFO_En bit is set to 1 and is cleared auto- matically after a transaction completes with an ACK or STALL. 0: The non-isochronous endpoint FIFO is disabled. 1: The non-isochronous endpoint FIFO is enabled.
Page 839: Receive Fifo Status Register (Rxfstat)
Register Map 13.2.6 Receive FIFO Status Register (RXFSTAT) The read-only receive FIFO status register (RXSTAT) tells how many bytes are in the receive FIFO for the selected endpoint. A write to this register has no effect. The local host cannot read this register if EP_Sel bit is not set for the endpoint.
Page 840 Register Map 13.2.7.1 Device Configuration Locked (Cfg_lock) After the local host has entered the device configuration (registers 0x20 to 0x3F), it must set this bit so that the device can be used. If the device configura- tion is not locked, the device is not ready to be used. 0: Device configuration is not locked.
Page 841: System Configuration Register 2 (Syscon2)
Register Map 13.2.7.5 External Pullup Enable (Pullup_En) Allows the device to disconnect itself from the USB bus, forcing the host to reset and reconfigure the device. This bit can be used to prevent USB traffic when the device is not ready. 0: Pullup disabled.
Page 842 Register Map 13.2.8.2 Stall Command (Stall_Cmd) Only concerns non-autodecoded requests on control endpoint (EP0). This is asserted in response to a USB command where either the command itself or its data is invalid. Asserting this bit forces the non-autodecoded com- mand to complete with a STALL handshake.
Page 843: Device Status Register (Devstat)
Register Map 13.2.9 Device Status Register (DEVSTAT) The read-only device status register (DEVSTAT) provides a status reflecting the visible device states as defined in USB1.1 chapter 9. A write to this register has no effect. This register is double buffered. If the DS_Chg_IE bit is set (interrupt enabled), the background register is moved to foreground position only after clearing any pending DS_Chg interrupts.
Page 844 Register Map 13.2.9.2 USB Reset Signaling (USB_Reset) This bit returns 1 when the USB host is resetting the USB bus. A valid USB reset resets all the endpoint FIFOS, all other control register bits except Cfg_Lock, all associated configuration registers (0x20 to 0x3F), and bits DS_Chg_IE and DS_Chg.
Page 845 Register Map 13.2.9.5 Addressed State (ADD) Device is attached to the USB and powered, has been reset, and a unique device address has been assigned. This bit returns 1 after a SET_ADDRESS standard request. This bit remains set to 1 until the device becomes de-addressed.
Page 846: Start Of Frame Register (Sof)
Register Map 13.2.10 Start of Frame Register (SOF) The read-only start of frame register (SOF) provides a frame timer status for use in isochronous communications. A write to this register is forbidden. Table 13–11. Start of Frame Register (SOF) Name Description 15–13 –...
Page 847: Interrupt Enable Register (Irq_En)
Register Map 13.2.10.2 Time Stamp OK(TS_OK) This bit indicates that the time stamp in the TS field is valid for the current frame. It returns a 1 if a valid SOF packet was received from the USB host and a 0 otherwise. 0: Time stamp is invalid.
Page 848: Interrupt Source Register (Irq_Src)
Register Map 13.2.12 Interrupt Source Register (IRQ_SRC) The read/clear-only interrupt source register (IRQ_SRC) has for function to identify and clear the source of the interrupt signaled by a set flag. Table 13–13. Interrupt Source Register (IRQ_SRC) Name Description 15–11 – Reserved TXn_Done Transmit DMA channel n done interrupt flag (non-isochronous)
Page 849 Register Map 13.2.12.1 Transmit DMA CH.n Done Interrupt Flag (TXn_Done) Only for non-isochronous DMA transfer. This bit is never set for isochronous DMA transfer. This bit is set automatically by the core when a transmit DMA channel has com- pleted the programmed transfer by servicing the last IN transaction from the USB host.
Page 850 Register Map 13.2.12.3 Receive DMA CH.n EOT Interrupt Flag (RXn_EOT) Only for non-isochronous DMA transfer. This bit is never set for isochronous DMA transfer. This bit is set automatically by the core when a receive DMA channel has detected an end of transfer (EOT) packet during the last OUT transaction from the USB host.
Page 851 Register Map 13.2.12.5 OUT Transaction Endpoint n Interrupt Flag (EPn_RX) Only concerns non-isochronous endpoints. This bit is automatically set by the core when a handshake sequence occurs for an OUT transaction to an interrupt of bulk endpoint (NAK with the Nak_En bit set, ACK, or STALL).
Page 852 Register Map 13.2.12.9 OUT Transaction Endpoint 0 Interrupt Flag (EP0_RX) This bit is set automatically by the core when a handshake sequence occurs for a non-autodecoded OUT transaction to control endpoint (NAK with the Nak_En bit set, ACK, or STALL). 0: No action 1: OUT transaction on EP0 Value after local host or USB reset is low.
Page 853: Non-Isochronous Endpoint Interrupt Status Register (Epn_Stat)
Register Map 13.2.13 Non-Isochronous Endpoint Interrupt Status Register (EPN_STAT) read-only non-isochronous endpoint interrupt status register (ENP_STAT) identifies the non-isochronous endpoint causing an EPn inter- rupt. A write into it is forbidden. If a non-transparent transaction occurs before a previous one on another end- point in the same direction has been handled by the local host, the second interrupt is asserted only after first one has been cleared by the local host and EPN_STAT is updated with the corresponding interrupt assertion.
Page 854: Non-Isochronous Dma Interrupt Status Register (Dman_Stat)
Register Map 13.2.14 Non-Isochronous DMA Interrupt Status Register (DMAN_STAT) The read-only non-isochronous DMA interrupt status register (DMAN_STAT) identifies the endpoint causing a DMA interrupt. A write into it is forbidden. If a DMA interrupt occurs before a previous one on another endpoint in the same direction has been handled by the local host, the second interrupt is asserted only after first one has been cleared by the local host and DMAN_STAT is updated when the corresponding interrupt is asserted.
Page 855: Receive Dma Channels Configuration Register (Rxdma_Cfg)
Register Map 13.2.14.2 DMA Receive Interrupt Source (DMAn_RX_IT_src) Only concerns non-isochronous endpoints. When the EPn_RX flag bit is set, the endpoint causing this flag to be set is encoded in these four register bits. When the EPn_RX flag bit is cleared, the four bits read as 0.
Page 856: Receive Dma Channels Configuration Register (Rxdma_Cfg)
Register Map Table 13–16. Receive DMA Channels Configuration Register (RXDMA_CFG) Name Description 15–12 – Reserved 11–8 RXDMA2_EP Receive endpoint number for DMA channel 2 7–4 RXDMA1_EP Receive endpoint number for DMA channel 1 3–0 RXDMA0_EP Receive endpoint number for DMA channel 0 13.2.15.1 Receive Endpoint Number for DMA Channel 2 (RXDMA2_EP) The endpoint number binary-encoded in these four bits is the current receive endpoint selected for DMA channel 2.
Page 857: Transmit Dma Channels Configuration Register (Txdma_Cfg)
Register Map 13.2.15.3 Receive Endpoint Number for DMA Channel 0 (RXDMA0_EP) The endpoint number binary encoded in these four bits is the current receive endpoint selected for DMA channel 0. A zero value indicates that the DMA channel 0 is deactivated. Any other value automatically enables receive DMA transfer for the selected endpoint.
Page 858 Register Map 13.2.16.1 Transmit Endpoint Number for DMA Channel 2 (TXDMA2_EP) The endpoint number binary-encoded in these four bits is the current transmit endpoint selected for DMA channel 2. A zero value indicates that the DMA channel 2 is deactivated. Any other value automatically enables transmit DMA transfer for the selected endpoint.
Page 859: Dma Fifo Data Register (Data_Dma)
Register Map 13.2.17 DMA FIFO Data Register (DATA_DMA) The DMA FIFO data register (DATA_DMA) is the entry point to write or to read data into/from an endpoint used in a DMA transfer through DMA channel 0, 1, or 2. Table 13–18. DMA FIFO Data Register (DATA_DMA) Name Description 15–0...
Page 860: Transmit Dma Control Registers (Txdma0
Register Map 13.2.18 Transmit DMA Control Registers (TXDMA0...TXDMA2) The read/write transmit DMA control registers (TXDMA...TXDMA2) control the operation of the transmit DMA channel n (n = 0, 1, 2). Table 13–19. Transmit DMA Control Registers (TXDMA...TXDMA2) Name Description TXn_EOT Transmit DMA channel n end of transfer TXn_Start Transmit DMA channel n start 13–10...
Page 861 Register Map 13.2.18.3 Transmit DMA Ch.n Transfer Size Counter (TXn_TSC) The binary-encoded value from 0 to 1023, which is written by the local host into this register, corresponds to the number of bytes or number of buffer transfers (function of TXn_EOT), which is transmitted by the transmit DMA channel n. When read, the register reflects the number of bytes/buffers the USB device has left to transmit.
Page 862: Receive Dma Control Registers (Rxdma
Register Map 13.2.19 Receive DMA Control Registers (RXDMA...RXDMA2) These read/write receive DMA control registers enable monitoring of incoming OUT transactions during DMA transfer on channel n (n=0,1,2). Table 13–20. Receive DMA Control Registers (RXDMA0...RXDMA2) Name Description RXn_Stop Receive DMA channel n transfer stop 14–8 –...
Page 863: Endpoint 0 Configuration Register (Ep0)
Register Map 13.2.20 Endpoint 0 Configuration Register (EP0) The read/write endpoint 0 configuration register (EP0) gives the device config- uration for control endpoint 0. Table 13–21. Endpoint 0 Configuration Register (EP0) Name Description 15–14 – Reserved 13–12 EP0_Size Endpoint 0 FIFO size –...
Page 864: Receive Endpoint Configuration Registers (Ep1_Rx
Register Map Set the pointer value higher than 0xFF, because the memory size is 2K bytes. A pointer value equal to 0xFF corresponds to 2040 bytes: addressing upper bytes results in memory overlap (see Section 13.4, Device Initialization). 13.2.21 Receive Endpoint Configuration Registers (EP1_RX...EP15_RX) The read/write receive endpoint configuration registers (EP1_RX...EP15_RX) give the device configuration for non-control receive endpoint n (n: 115).
Page 865: Endpoint N Size Values
Register Map 13.2.21.2 Receive Endpoint n Double-Buffer (EPn_RX_Db) This bit is only for non-isochronous endpoints. For isochronous endpoints, which are always double-buffered, this bit is endpoint size MSB. This bit must be set by the local host to allow double buffering for receive non-isochronous endpoint n.
Page 866 Register Map 13.2.21.4 Receive Isochronous Endpoint n(EPn_RX_Iso) This field must be set if the receive endpoint n type is isochronous in the desired device configuration. If not set, the endpoint type is bulk or interrupt (the hardware does not distinguish bulk type from interrupt). 0: Receive endpoint n type is isochronous.
Page 867: Transmit Endpoint Configuration Registers (Ep1_Tx
Register Map 13.2.22 Transmit Endpoint Configuration Registers (EP1_TX...EP15_TX) The read/write transmit endpoint configuration registers (EP1_TX... EP15_TX) configure the device for noncontrol transmit endpoint n (n: 115). The endpoint size fields must match the values sent by the local host to the USB host in response to the GET_CONFIGURATION_DESCRIPTOR during configuration phase.
Page 868 Register Map 13.2.22.3 Transmit Endpoint n Size (EPn_TX_Size) EPn_TX.[14] bit description only applies for isochronous endpoints. This field contains the endpoint n FIFO size value. Status flags (FIFO_Empty, FIFO_Full) and underrun condition are based on this value for all IN transac- tions to endpoint n (see Table 13–23, Endpoint n Size Values).
Page 869: Usb Transactions
USB Transactions 13.3 USB Transactions There is an interrupt to the local host at the end of a USB transaction if the local host has actions to perform. Isochronous transactions are an exception, because isochronous interrupt information is available at start of frame inter- rupts.
Page 870: Non-Isochronous, Non-Control Out Endpoint Handshaking Conditions
USB Transactions Figure 13–3. Non-Isochronous, Non-Control OUT Endpoint Handshaking Conditions Successful data transfer from USB host. (Occurs because the endpoint’s STAT_FLG bits after STAT_FLG.FIFO_En bit was set when token was received.) interrupt Token Data EPx Rx Interrupt After interrupt, EP’s RX FIFO contains received data. STAT_FLG bits after No data accepted by DSP.
Page 871 USB Transactions 13.3.1.1 Non-Isochronous, Non-Control OUT Endpoint Handshaking Conditions The Set_FIFO_En bit provides the main control for the ability to allow success- ful OUT transaction data reception for the endpoint. If at the beginning of an OUT transaction to an endpoint the FIFO_En bit is 1, the USB module is al- lowed to accept the OUT transaction data to the RX FIFO and, when the trans- action completes, the USB module can return ACK to the USB host to indicate that the data was received correctly (this is the top case shown in Figure 13–3).
Page 872 USB Transactions Non-Acknowledged Transactions (NAK) The device can be configured via the Nak_En bit, either to inform the local host of a NAKed transaction or not. If the NAK_EN bit is cleared, no interrupt is asserted to the local host if an OUT transaction completes with a NAK hand- shake and the NAK bit not set.
Page 873 USB Transactions FIFO. If the EP_Halted has been set in response to a SET_FEATURE request sent by the USB host or if the bit is cleared (control transaction only), the local host has no action to perform and must clear the EP_Sel bit. This clears the STALL bit for this endpoint and allows the next transaction status to be written to the STAT_FLG register.
Page 874: Non-Isochronous In (Lh->Usb Host) Transactions
USB Transactions 13.3.2 Non-Isochronous IN (LH–>USB HOST) Transactions Non-isochronous IN transactions refer to USB transactions where data is moved from the local host to the USB host where the USB handshaking proto- cols are in effect and data transmission is guaranteed. These transactions are the IN transactions that occur on control, bulk, and interrupt endpoints.
Page 875: Non-Isochronous In Transaction Phases And Interrupts
USB Transactions Figure 13–4. Non-Isochronous IN Transaction Phases and Interrupts Successful data transfer to USB host (endpoint STAT_FLG.FIFO_En bit was set when token was received). STAT_FLG bits after interrupt IN Token Data Endpoint X TX interrupt After interrupt, endpoint TX FIFO is empty. No data transmitted by LH (endpoint STAT_FLG>FIFO_En bit was clear when STAT_FLG bits after token was received).
Page 876 USB Transactions 13.3.2.1 Non-Isochronous IN Endpoint Handshaking Per the USB spec for IN transactions, the USB host may only provide one of two handshakes to the USB function during the handshake phase: ACK or no handshake at all. The first indicates successful transfer (first case shown in Figure 13–4), and the second indicates that the host received a garbled data packet (last case shown in Figure 13–4).
Page 877 USB Transactions In response to the endpoint interrupt, the local host must read the EPN_STAT register to identify the endpoint causing the interrupt, then write a 1 to the inter- rupt bit to clear it. The local host must set EP_Num to the endpoint number, EP_Dir to 1 (to signal an IN endpoint), and EP_Sel to 1, then read the endpoint status.
Page 878: Isochronous Out (Usb Host-> Lh) Transactions
USB Transactions Except for control endpoint 0, separate endpoint halt bits are defined for each direction; so for a given endpoint number, the TX can be halted when the RX is not. Packet Errors If an error (CRC, bit stuffing or PID check) occurs during the token packet of a USB IN transaction to a non-isochronous endpoint, the USB block ignores the transaction.
Page 879: Isochronous Out Transaction Phases And Interrupts
USB Transactions side of the USB module is allowed to write to the background RX FIFO, and the local host is allowed to read to the foreground RX FIFO. The designations foreground and background are swapped at each start of frame (SOF). Isochronous endpoint FIFOs in the background are always enabled to the USB, while the foreground FIFOs are enabled to the local host.
Page 880: Isochronous In (Lh->Usb Host) Transactions
USB Transactions 13.3.3.2 Isochronous OUT Transaction Error Conditions If the local host fails to read all of the data in the isochronous OUT endpoint foreground FIFO by the time that the foreground and background FIFOs are switched (at the next SOF), the endpoint FIFO that is being switched to the background is flushed and the Data_Flush bit is asserted for the duration of the next frame.
Page 881: Isochronous In Transaction Phases And Interrupts
USB Transactions Because the USB transaction for the isochronous endpoint can occur at any time during the 1-ms USB frame, the USB interface implements a double buff- ering of the endpoint transmit data FIFO. The endpoint includes two FIFOs, each of which is the length of the configured isochronous endpoint. At all times, one of the two FIFOs is foreground and the other is background.
Page 882: Control Transfers On Endpoint 0
USB Transactions 13.3.4.1 Isochronous IN Endpoint Handshaking Because isochronous endpoint transactions have no handshake packets, the STALL, the NAK, and the ACK bits for isochronous endpoints always return 0. Because there is no handshake, there is no endpoint-specific interrupt to the local host to report handshake results for isochronous endpoints.
Page 883: Stages And Transaction Phases Of Autodecoded Control Transfers
USB Transactions Figure 13–7. Stages and Transaction Phases of Autodecoded Control Transfers Autodecode control write transfer–correct status (set address, clear/set device/interface feature). Setup Stage Status Stage Setup Status Completion Command Token Token Status Interrupt occurs/status flags are not updated. Autodecode control read transfers-–request error (due to wrong setup data).
Page 884: Stages And Transaction Phases Of Non-Autodecoded Control Transfers
USB Transactions Figure 13–8. Stages and Transaction Phases of Non-Autodecoded Control Transfers Non-autodecode control write transfers-–correct status Data Stage (Occurs 0 or more times, Setup Stage depending on the amount of data) Status Stage Setup Command Status Completion Command Token Token Data Token...
Page 885 USB Transactions Non-autodecoded control read and control write transfers are sets of transac- tions that occur on endpoint 0, have specific USB protocol meaning, and are not handled automatically by the core. The USB function block automatically provides an ACK handshake for the setup stage transaction, but the data and status stage transaction handshaking is accomplished using the normal RX and TX control bits that affect transaction handshaking.
Page 886 USB Transactions When a setup token is identified, the USB decode module must monitor the setup stage data packet, decode it, and determine if it is an autodecoded or a non-autodecoded transfer and a control read or a control write. If it is a valid non-autodecoded request, the setup FIFO is immediately cleared and control of the FIFO is immediately taken away from the local host (if the local host had control of the FIFO).
Page 887 USB Transactions 13.3.5.2 Autodecoded Control Read Transfers Autodecoded control reads include the standard device request to get the end- point and device status. These control read transfers access information that is kept in registers inside the USB module, so local host code is not involved in filling the read data into the TX FIFO.
Page 888 USB Transactions 13.3.5.3 Non-Autodecoded Control Write Transfers Non-autodecoded control write transfers include the set/clear endpoint feature, set configuration, set interface, set descriptor, and class- or vendor- specific control write transfers. Non-autodecoded control write transfers consist of two or three stages (setup, data (optional), and status). The setup stage of a valid non-autodecoded control write transfer consists of one SETUP transaction from USB host to USB device.
Page 889 USB Transactions Specific Local Host Required Actions If the device receives a valid set endpoint halt feature request, it must set the appropriate Set_Halt control bit. If the device receives a valid clear endpoint halt feature request, it must set the appropriate Reset_EP bit to clear halt condition, set FIFO flags, and reset data PID to DATA0 for the endpoint.
Page 890 USB Transactions Status stage handshaking is controlled by the endpoint 0’s FIFO_En and Stall_Cmd bits. Successful completion of a non-autodecoded control write transfer is indicated by the USB function module returning a zero-length data payload for the data phase of the status stage and an ACK handshake from the host for the handshake phase of the status stage.
Page 891 USB Transactions The data stage of a control read transfer consists of one or more IN transac- tions. Transaction handshaking and interrupt generation apply as for non- isochronous, non-control IN endpoints; the local host can cause NAK, STALL, or ACK signaling for the data stage transactions. At endpoint 0 TX general USB interrupts, local host code must move more data to the endpoint 0 FIFO until the last bytes of the requested data has been provided.
Page 892: Autodecoded Versus Non-Autodecoded Control Requests
USB Transactions Successful completion of non-autodecoded control read transfers is indicated by the host sending an OUT token followed by an empty packet and the USB function module responding with ACK. If the data packet sent by the USB host during the status stage of a control read request is not empty, the OUT trans- action is accepted by the core, but OUT data is not put into the endpoint 0 RX FIFO.
Page 893 USB Transactions Table 13–25. Autodecoded Versus Non-Autodecoded Control Requests (Continued) Device Behavior if Request Recipient Status LH Required Action Device not Configured CLEAR/SET Device Autodecoded None The core handles the FEATURE (DS_Chg interrupt is asserted to request. the local host after any the R_WK_OK bit modification).
Page 894 USB Transactions Table 13–25. Autodecoded Versus Non-Autodecoded Control Requests (Continued) Device Behavior if Request Recipient Status LH Required Action Device not Configured SET_ Non-autode- The local host must stall the Command is passed to the DESCRIPTOR coded command (via the Stall_Cmd local host.
Page 895 USB Transactions Transactions on endpoints other than zero are ignored if the device is not configured (addressed state). If some endpoints are not used by the interface currently set, transactions on these endpoints are not ignored; the local host must set the Halt feature for the endpoint.
Page 896: Device Initialization
Device Initialization 13.4 Device Initialization To allow communication between the device and a USB host, the local host must configure the device by filling the configuration registers. For each endpoint, the local host must write to dedicated register: Endpoint size Whether or not double buffering is allowed for endpoint Endpoint type (isochronous or non-isochronous) Address of the pointer...
Page 897: Example Of Ram Organization
Device Initialization Figure 13–9. Example of RAM Organization Setup Data (8 bytes) EP0_ptr EP0_Size Endpoint0 Data EP1_RX_ptr EP1_RX_Size or 2*EP1_RX_Size (if Endpoint1 RX Data Double Buffering or ISO) EP2_RX_ptr EP2_RX_Size or 2*EP2_RS_Size (if Endpoint2 RX Data Double Buffering or ISO) EP3_RX_ptr EP15_RX_ptr EP15_RX_Size or...
Page 898: Device Configuration Routine
Device Initialization Figure 13–10. Device Configuration Routine Enter Device Configuration Routine Configured endpoint values must match values returned in descriptors during the enumeration phase. Endpoint Configuration After a USB reset, all IRQ_EN registers except DS_Chg are cleared. They must be re- Fill IRQ_EN register with enabled.
Page 899: Endpoint Configuration Routine
Device Initialization Figure 13–11. Endpoint Configuration Routine Enter Endpoint Configuration Routine Set Ptr_flag to 8 Fill EP0 register with – EP0_Size – EP0_ptr=Ptr_flag Ptr_flag = Ptr_flag + EP0_Size Fill EPn_RX register with: Another Any OUT Ptr_flag = – EPn_RX_Valid = 1 Endpoint n is OUT endpoint endpoint to...
Page 900: Preparing For Transfers
Preparing for Transfers 13.5 Preparing for Transfers To avoid NAK handshakes for the first transaction on an endpoint, the local host must prepare the endpoint FIFO for receiving or transferring data. After the first transaction, the FIFO is enabled during the interrupt handling. For receive endpoints, this phase consists of enabling the FIFO to receive data from the USB host.
Page 901: Prepare For Usb Rx Transfer Routine
Preparing for Transfers Figure 13–12. Prepare for USB RX Transfer Routine This enables both Prepare for USB FIFOs if double-buffering RX transfers Note: This applies to all non- is used. routine ISO endpoints, with or without DMA. Write EP_NUM register: –...
Page 902: Prepare For Tx Transfer On Endpoint N Routine
Preparing for Transfers Figure 13–13. Prepare for TX Transfer on Endpoint n Routine Prepare for USB TX Transfer on Endpoint n routine This does not apply to TX endpoints using DMA, which are enabled when TXDMAn.Start is set by the LH. Write EP_NUM register: –...
Page 903: Interrupt Service Routine (Isr) Flowcharts
Interrupt Service Routine (ISR) Flowcharts 13.6 Interrupt Service Routine (ISR) Flowcharts The flowcharts in this section give general operational guidelines for USB ISR processing. System-architecture-specific details are left to the engineers who write the local host and USB host code. One USB-specific interrupt register is provided (IRQ_SRC) to keep track of the interrupts to handle.
Page 904: Parsing The General Usb Interrupt
Interrupt Service Routine (ISR) Flowcharts an ACKed transaction. If double buffering is used for an endpoint, the status flag register is updated if there is zero or one interrupt pending for the endpoint and is not updated if there are already two interrupts pending on the endpoint. The local host does not need to set the Nak_En bit during normal operation.
Page 905: General Usb Interrupt Isr Source Parsing Flowchart
Interrupt Service Routine (ISR) Flowcharts Figure 13–14. General USB Interrupt ISR Source Parsing Flowchart Enter General USB The interrupt must be cleared within the device state changed handler. USB Device State Changed Handler IRQ_SRC.Chg EP0 RX IRQ_SRC. IRQ_SRC.EP0_RX EP0_RX = 1 Handler to clear the IT.
Page 906: Setup Interrupt Handler
Interrupt Service Routine (ISR) Flowcharts Figure 13–15. Setup Interrupt Handler Setup stage handler Application-specific Clear control action to cancel any flags. ongoing transfer Parse command wlength_count = wlenght Is the request SYSCON2.Stall_Cm legal and d to 1 to stall next supported? EP0 transaction.
Page 907: Parse Command Routine (Setup Stage Control Transfer Request)
Interrupt Service Routine (ISR) Flowcharts Figure 13–16. Parse Command Routine (Setup Stage Control Transfer Request) Parse command routine This clears the IRQ_SRC.Setup bit. Write EP_NUM register: – EP_NUM.EP_Num = 0 – EP_NUM.EP_Dir = 0 – EP_NUM.EP_Sel = 0 – EP_NUM.Setup_Sel = 1 Read byte from DATA Save bmRequest type register.
Page 908: Endpoint 0 Rx Interrupt Handler
Interrupt Service Routine (ISR) Flowcharts 13.6.4 Endpoint 0 RX Interrupt Handler The endpoint 0 RX portion of the general USB interrupt handler, shown in Figure 13–17, must handle general USB interrupts related to control OUT transactions on endpoint 0. Notice that no EP0 interrupt is generated for autodecoded control transfers.
Page 909: Endpoint 0 Rx Interrupt Handler
Interrupt Service Routine (ISR) Flowcharts Figure 13–17. Endpoint 0 RX Interrupt Handler Endpoint 0 RX handler Write EP_NUM register: – EP_NUM.EP_Num = 0 – EP_NUM.EP_Dir = 0 – EP_NUM.EP_Sel = 1 – EP_NUM.Setup_Sel = 0 Write EP_NUM register: Application- Control –...
Page 910: Prepare For Control Write Status Stage Routine
Interrupt Service Routine (ISR) Flowcharts Figure 13–18. Prepare for Control Write Status Stage Routine Prepare for control This actions include: write stage status Reset-relevant endpoints if request is clear routine endpoint feature, set config, or set interface. Set halt for relevant endpoints if request is set endpoint feature, set config, or set interface.
Page 911: Endpoint 0 Tx Interrupt Handler
Interrupt Service Routine (ISR) Flowcharts Figure 13–19. Endpoint 0 TX Interrupt Handler Endpoint 0 TX fandler Write EP_NUM register: – EP_NUM.EP_Num = 0 – EP_NUM.EP_Dir = 1 – EP_NUM.EP_Sel = 1 – EP_NUM.Setup_Sel = 0 Write EP_NUM register: Application- Control –...
Page 912: Prepare For Control Read Status Stage Routine
Interrupt Service Routine (ISR) Flowcharts Figure 13–20. Prepare for Control Read Status Stage Routine Prepare for control read status stage routine Application- specific actions to determine control read action and status result Write EP_NUM register: Set CTRL.Clr_EP to – EP_NUM.EP_Num = 0 Want to respond 1, then set –...
Page 913: Device States Changed Handler
Interrupt Service Routine (ISR) Flowcharts 13.6.6 Device States Changed Handler This section describes how USB device states and transitions states are decoded by the USB function and how they can be handled. The state machine (see Figure 13–21) moves the USB function device from one state to another state with respect to USB1.1 specification.
Page 914: Usb Function Device State Transitions
Interrupt Service Routine (ISR) Flowcharts Figure 13–21. USB Function Device State Transitions ATTACHED USB RESET ‡ SET_ADDRESS 0 USB RESET ‡ SET_CONFIGURATION Remote wake α † up enabled DEFAULT SET_ADDRESS 0 SUSPEND USB RESET SET_ADDRESS < > 0 ‡ Remote wake up enabled SET_ADDRESS <...
Page 915: Typical Operation For Usb Device State Changed Interrupt Handler
Interrupt Service Routine (ISR) Flowcharts Figure 13–22. Typical Operation for USB Device State Changed Interrupt Handler Device state changed handler Read DEVSTAT register (new value), read DS_mem (previous value). Attached/ DEVSTAT. umattached ATT changed? Device state must be handler at least attached at this point.
Page 916: Device States Attached/Unattached Handler
Interrupt Service Routine (ISR) Flowcharts 13.6.7 Device States Attached/Unattached Handler The device attached/unattached interrupt (Figure 13–23) occurs either when the device etects it is connected to the USB host or Hub (VBUS is on) or when it becomes disconnected (VBUS is off). The local host can use this interrupt to put the evice into deep sleep or to initialize any application-specific informa- tion relating to the USB device.
Page 917: Usb Reset Interrupt Handler
Interrupt Service Routine (ISR) Flowcharts 13.6.8 USB Reset Interrupt Handler When a USB reset occurs, the USB module generates a general USB interrupt to the local host (see Figure 13–24 and Figure 13–25). The local host responds to this interrupt by performing the following operations: Cancels any ongoing USB transaction and/or control transfer handling Clears any copies that the application has of configuration number or of alternate interface numbers...
Page 918: Usb Reset Handler Flowchart I
Interrupt Service Routine (ISR) Flowcharts Figure 13–24. USB Reset Handler Flowchart I USB reset handler Inform application that the USB DEVSTAT. USB_Reset reset has completed = 1? and that device is in default state. Clear endpoint’s transaction and control transfer flags. Application- Application- specific actions...
Page 919: Usb Reset Handler Flowchart Ii
Interrupt Service Routine (ISR) Flowcharts Figure 13–25. USB Reset Handler Flowchart II USB reset handler Inform application that the USB DEVSTAT. USB_Reset reset has completed = 1 ? and that device is in default state. Clear endpoint transaction and control transfer flags. Application- Application- specific actions...
Page 920: Typical Operation For Usb Suspend/Resume General Usb Interrupt Handler
Interrupt Service Routine (ISR) Flowcharts Figure 13–26. Typical Operation for USB Suspend/Resume General USB Interrupt Handler Suspend/resume handler Inform Set IRQ_SRC.DS application that DEVSTAT.SUS _Chg = 1 device is = 1? entering to clear the IT. suspend. Read DEVSTAT.R_Wk_ Inform OK value.
Page 921: Non-Isochronous Endpoint-Specific (Except Er 0) Isr Flowchart
Interrupt Service Routine (ISR) Flowcharts Figure 13–27. Non-Isochronous Endpoint-Specific (Except ER 0) ISR Flowchart Enter non_ISO endpoint-specific ISR Write EP_NUM register: Read endp_nb value Write 1 to – EP_NUM.EP_Num = endp_nb IRQ_SRC. from EPN_STAT. IRQ_SRC.EPn_RX to – EP_NUM.EP_Dir = 0 EPn_RX = 1? EPn_RX_IT_src.
Page 922: Non-Isochronous, Non-Control Out Endpoint Receive Interrupt Handler
Interrupt Service Routine (ISR) Flowcharts 13.6.11 Non-Isochronous, Non-Control OUT Endpoint Receive Interrupt Handler Figure 13–28 shows the operations necessary to handle non-isochronous, non-control OUT endpoint-specific receive interrupts. This flowchart shows two different RX transaction handshaking interrupts. There is a third interrupt handshaking possibility when NAK interrupts are enabled, which is not depicted here.
Page 923: Non-Isochronous Non-Control Endpoint Receive Interrupt Handler
Interrupt Service Routine (ISR) Flowcharts Figure 13–28. Non-Isochronous Non-Control Endpoint Receive Interrupt Handler Non-ISO RX handler (NAK disabled) Application- STAT_FLG. specific Read Non-ISO ACK = 1? preparation to packet from (Data packet RX FIFO data. receive received?) endpoint data No. Must be STAT_FLG.STALL LH-initiated Application- Set RXCON1.Clr_Halt...
Page 924: Read Non-Isochronous Rx Fifo Data Flowchart
Interrupt Service Routine (ISR) Flowcharts Figure 13–29. Read Non-Isochronous RX FIFO Data Flowchart Read non-ISO RX FIFO data STAT_FLG. Set FIFO not full and DB EPn_RX.EPn_RX_ non_ISO FIFO to 1. Size or DB _Empty = 1? = 1? STAT_FLG. Read received bytes EPn_RX.EPn_RX_ Non_ISO_FIFO count in...
Page 925: Non-Isochronous Non-Control Endpoint Transmit Interrupt Handler
Interrupt Service Routine (ISR) Flowcharts Figure 13–30. Non-Isochronous Non-control Endpoint Transmit Interrupt Handler TX data that was previously placed in the endpoint’s TX FIFO remains in the application’s buffer until that data is properly Non-ISO TX handler sent to the USB host and receives an ACK. Caution: If double-buffer is used, the local host must retire (NAK disabled from its buffer the first packet that was written into TX FIFO.
Page 926: Write Non-Isochronous Tx Fifo Data Flowchart
Interrupt Service Routine (ISR) Flowcharts Figure 13–31. Write Non-Isochronous TX FIFO Data Flowchart Write non-ISO TX FIFO data The loop count must be set to 0 for sending an empty data packet. Set loop count to # bytes in application’s TX buffer.
Page 927: Sof Interrupt Handler Flowchart
Interrupt Service Routine (ISR) Flowcharts Figure 13–32. SOF Interrupt Handler Flowchart SOF ISR entry Application- specific SOF timing handling Write EP_NUM register: Any ISO RX – EP_NUM.EP_Num = n endpoint ISO RX – EP_NUM.EP_Dir = 0 configured? Handler – EP_NUM.EP_Sel = 1 (EPn) –...
Page 928: Read Isochronous Rx Fifo Data Flowchart
Interrupt Service Routine (ISR) Flowcharts Figure 13–33. Read Isochronous RX FIFO Data Flowchart ISO RX handler Application- specific actions STAT_FLG. to handle case Data_Flush for data flush Application- specific actions STAT_FLG. to handle ISO_Error unrecovered ISO packet Application- specific actions to handle STAT_FLG.
Page 929: Write Isochronous Tx Fifo Data Flowchart
Interrupt Service Routine (ISR) Flowcharts Figure 13–34. Write Isochronous TX FIFO Data Flowchart ISO TX handler When a Missed_in occurs, missed data are from TWO frames previous). Application- specific actions to handle Wish to resend CTRL.Cir_EP to STAT_FLG. missed data? missed in data Miss_In clear the current...
Page 930: Usb Interrupt Type By Endpoint Type
Interrupt Service Routine (ISR) Flowcharts 13.6.14 Summary of USB-Related Interrupts Table 13–26. USB Interrupt Type by Endpoint Type General USB IRQs EP-Specific IRQs Control Control Bulk or Bulk or (EP0) (EP0) Interrupt Interrupt Setup (Isochronous) (EP0) Other Interrupt Type √ √...
Page 931: Dma Operation
DMA Operation 13.7 DMA Operation The USB function module provides support for six DMA channels. Three receive DMA channels are reserved for OUT transfers (isochronous or non- isochronous) and three transmit DMA channels are reserved for IN transfers (isochronous or non-isochronous). It is not possible to operate DMA trans- actions on control EP0.
Page 932: Non-Isochronous Rx Dma Transaction Example (Rx_Tc = 2)
DMA Operation After an end of transfer interrupt, the local host must set the Set_FIFO_ En for the endpoint to reenable the channel. The local host must not initiate a new RX DMA transfer until it receives an end-of-transfer interrupt. Transactions count interrupt (the RXn_Cnt) This interrupt performs watermark control.
Page 933: Non-Isochronous Rx Dma Start Routine
DMA Operation Figure 13–36. Non-Isochronous RX DMA Start Routine Endpoints assigned to a DMA Non-ISO RXDMA[0, 1, 2] channel must have been configured start routine during endpoint configuration phase. Assign non-ISO endpoint −−> EP number number to DMA channel n. RXDMA_CFG.
Page 934: Non-Isochronous Rx Dma Eot Interrupt Handler
DMA Operation Figure 13–37. Non-Isochronous RX DMA EOT Interrupt Handler Non-ISO RX DMA EOT handler Read endpoint number in DMAN_STAT. DMAn_RX_IT_src register. Read DMAN_STAT. DMAn_RX_SB register to be informed of an odd number of bytes for last transaction. Inform the application that the RX DMA transfer on channel n is completed.
Page 935: Non-Isochronous Rx Dma Transaction Count Interrupt Handler
DMA Operation Figure 13–38. Non-Isochronous RX DMA Transaction Count Interrupt Handler Non-ISO RX DMA count handler Read channel number n in DMAN_STAT. DMAn_RX_IT_src register. Inform the application that the RX DMA transfer on channel n has sent RXDMAn.RXn_TC transaction count without detecting an EOT.
Page 936: Isochronous Out (Usb Host -> Lh) Dma Transactions
DMA Operation 13.7.3 Isochronous OUT (USB HOST −> LH) DMA Transactions During isochronous transfers to a DMA-operated OUT endpoint, a request to the local host DMA controller is generated every 1-ms frame when an isochro- nous data packet is received with no error. There is no interrupt associated with DMA transfer to isochronous OUT endpoints.
Page 937: Transmit Dma Channels Overview
DMA Operation 13.7.4 Transmit DMA Channels Overview Transmit DMA channels are programmed via the three TXDMA control regis- ters. Each channel can be assigned to a given endpoint number by assigning a nonzero value in TXDMAn_EP (a 0 value means the DMA channel is deselected).
Page 938: File Transfer Size
DMA Operation The size of the file to transfer (FTZ) can be assimilated conceptually as a concatenation of three arguments as shown in Figure 13–41. Figure 13–41. File Transfer Size FTZ (File transfer size) XSWL EOTB XSWL (Extra software FBT (Full buffer EOTB (End of transfer Loop –...
Page 939: Non-Isochronous Tx Dma Dma Start Routine
DMA Operation Figure 13–42. Non-Isochronous TX DMA DMA Start Routine Non-ISO TXDMA[0, 1, 2] start routine Assign non-ISO endpoint number to DMA channel n. EP number −−> TXDMA_CFG. TXDMAn_EP. LH DMA write access must point to TXDCHn.TXDATn in response to DMA Application-specific channel n request.
Page 940: Non-Isochronous Tx Dma Done Interrupt Handler
DMA Operation Figure 13–43. Non-Isochronous TX DMA Done Interrupt Handler Non-ISO TX DMA done handler Read the endpoint umber n in DMAN_STAT. DMAn_TX_IT_src register. IRQ_SRC.TXn_Done = 1 to clear the IT. Inform the application that EOTn = 1? the TX DMA transfer is completed.
Page 941: Isochronous In (Usb Host -> Lh) Dma Transactions
DMA Operation 13.7.6 Isochronous IN (USB HOST −> LH) DMA Transactions For isochronous endpoints (Figure 13–44), the transfer size counter (TXn_TSC) corresponds to the number of bytes to transmit. The programmed size must not exceed the programmed buffer size of the endpoint; otherwise the results are unpredictable.
Page 942: Isochronous Tx Dma Start Routine
DMA Operation Figure 13–44. Isochronous TX DMA Start Routine ISO TXDMA[0,1, 2] start routine Assign ISO endpoint number to DMA channel n. EP number −−> TXDMA_CFG. TXDMAn_EP LH DMA write access must point to TXDCHn.TXDATn in response to DMA Application-specific channel n request.
Page 943: Note On Dma Channel Deconfiguration
DMA Operation 13.7.8 Note on DMA Channel Deconfiguration It is recommended that the local host wait for an EOT (RX) or a done (TX) in- terrupt before disabling the channel by writing a value 0 in TX/RXDMA_CFG register. However, if needed by the application, the local host can deselect the endpoint number in the TX/RXDMA_CFG register during a DMA transfer.
Page 944: Power Management
Power Management 13.8 Power Management The flowchart in Figure 13–45 shows the values assigned to USB function signals concerned with power management in the functioning of the device state. These signals are: PUEN_O Pullup enable signal, which always reflects the Pullup_En register bit. SHUTOFF_O Power circuitry shutoff signal, controlled by the core and the SOFF_Dis bit.
Page 945: Power Management Signal Values
Power Management Figure 13–45. Power Management Signal Values Device not powered not attached to USB Power on USB cable inserted PUEN_O = 0 SUSPEND_O = 1 No power † SHUTOFF_O = 1 DS_WAKE_REQ_ON = 1 LH sets SYSCON1. Pullup_En. USB cable inserted PUEN_O = 1 PUEN_O = 0 SUSPEND_O = 1...
Page 946: Universal Serial Bus Host
Chapter 14 Universal Serial Bus Host This chapter describes the universal serial bus (USB) host of the OMAP5910 multimedia processor. Topic Page 14.1 USB Host Controller ......... .
Page 947: Usb Host Controller
Interface Specification for USB, Release 1.0a, available through the Com- paq Computer Corporation web site, and hereafter called the OHCI Specifica- tion for USB. It is assumed that users of the OMAP5910 USB host controller are already familiar with the USB Specification and OHCI Specification for USB.
Page 948: Omap5910 Usb Host Controller Block Diagram
USB Host Controller OMAP5910 pins associated with the integrated USB transceiver are only available for use by the OMAP5910 USB host controller or OMAP5910 USB function controller and are not shared with any other peripherals. Figure 14–1 shows the OMAP5910 device with the USB host controller high- lighted.
Page 949: Omap5910 Usb Host Controller
USB Host Controller Figure 14–2. OMAP5910 USB Host Controller MPU public peripheral bus Peripheral UART 1 function controller INTH2 Peripheral protection Peripheral MPU Public peripheral interface Local Bus interface Local bus MPU’s controller Memory LB’s USB Host Controller controller Signals to/from other...
Page 950: Usb Open Host Controller Interface Functionality
USB host controller interfaces to system software. This specification, in conjunction with the Universal Serial Bus Specification Version 1.1, define most of the USB functionality that the OMAP5910 USB host controller provides. The OHCI Specification for USB focuses on two main aspects of the hardware implementation of a USB host controller: its register set and the memory data structures that define the activity to appear on the USB bus.
Page 951 USB Open Host Controller Interface Functionality 14.2.2.2 Overcurrent Protection Input Pins Not Supported The OMAP5910 device does not provide any pins that allow the USB host con- troller OHCI RhPortStatus(n) overcurrent protection status bits to be directly controlled by external hardware.
Page 952: Omap5910 Implementation Of Ohci Specification For Usb
EDs. If any of these pointers are NULL when the corresponding list enable bit is set, the OMAP5910 USB host control- ler attempts to access using the local bus virtual address of 0, which causes an unrecoverable error.
Page 953: Usb Host Controller Registers
¶ This register provides control and status for the OMAP5910 pins associated with USB port 1 for some HMC_MODE values. # This register provides control and status for the OMAP5910 pins associated with USB port 2 for some HMC_MODE values.
Page 954 ¶ This register provides control and status for the OMAP5910 pins associated with USB port 1 for some HMC_MODE values. # This register provides control and status for the OMAP5910 pins associated with USB port 2 for some HMC_MODE values.
Page 955: Ohci Revision Number Register (Hcrevision)
Reserved Reserved Remote wake-up enable. This bit has no effect in OMAP5910. The OMAP5910 USB host controller does not provide a processor wake-up mechanism. Remote wake up connected. This bit has no effect in OMAP5910. The OMAP5910 USB host controller does not provide a processor wake-up mechanism.
Page 956 USB Host Controller Registers Table 14–3. HC Operating Mode Register (HcControl) (Continued) Reset Name Value Description Type Value 7–6 HCFS Host controller functional state: USBReset USBResume USBOperational USBSuspend A transition to USBOperational causes SOF generation to begin in 1 ms. The USB host controller may automatically transition from USBSuspend to USBResume if a downstream resume is received.
Page 957 USB Host Controller Registers Table 14–3. HC Operating Mode Register (HcControl) (Continued) Reset Name Value Description Type Value Isochronous enable Enables processing of isochronous EDs. Isochronous EDs are not processed. The USB host controller checks this bit every time it finds an isochronous ED in the periodic list.
Page 958: Hc Command And Status Register (Hccommandstatus)
Ownership change request This bit is set by the host controller driver to gain ownership of the host controller. OMAP5910 does not support SMI interrupts, so no ownership change interrupt occurs. Bulk list filled The host controller driver must set this bit if it modifies the bulk list to include new TDs.
Page 959: Hc Interrupt Status Register (Hcinterruptstatus)
Reset Name Description Type Value Reserved Reserved Ownership change The OMAP5910 USB host controller does not implement ownership change interrupts. 29 –7 Reserved Reserved RHSC Root hub status change When 1 indicates a root hub status change has occurred. Write of 0 has no effect.
Page 960: Hc Interrupt Enable Register (Hcinterruptenable)
Write of 0 has no effect. Write of 1 clears this bit. The HC interrupt enable register enables various OHCI interrupt sources to generate interrupts to the OMAP5910 level 2 interrupt handler. Table 14–6. HC Interrupt Enable Register (HcInterruptEnable) Reset...
Page 961 RHSC Root hub status change When 1 and MIE is 1, allows root hub status change interrupts to propagate to the OMAP5910 level 2 interrupt controller. When 0, or when MIE is 0, root hub status change interrupts do not propagate.
Page 962 A write of 1 sets this bit. Scheduling overrun When 1 and MIE is 1, allows scheduling overrun interrupts to propagate to the OMAP5910 level 2 interrupt controller. When 0, or when MIE is 0, scheduling overrun interrupts do not propagate.
Page 963: Hc Interrupt Disable Register (Hcinterruptdisable)
Value Master interrupt enable Read always returns 0. Write of 0 has no effect. Write of 1 clears the HcInterruptEnable MIE bit. Ownership change This bit has no effect on OMAP5910. 29–7 Reserved Reserved RHSC Root hub status change Read always returns 0.
Page 964: Hc Hcaa Address Register (Hchcca)
USB Host Controller Registers Table 14–7. HC Interrupt Disable Register (HcInterruptDisable) (Continued) Reset Name Description Type Value Write done head Read always returns 0. Write of 0 has no effect. Write of 1 clears the HcInterruptEnable WDH bit. Scheduling overrun Read always returns 0.
Page 965: Hc Head Control Register (Hccontrolheaded)
USB Host Controller Registers The HC head control register defines the local bus virtual address of the head ED of the control ED list. Table 14–10. HC Head Control Register (HcControlHeadED) Reset Name Description Type Value 31–4 CHED Local bus virtual address of head ED on the control ED list This field represents bits 31:4 of the local bus virtual address of the head ED on the control ED list.
Page 966: Hc Head Bulk Register (Hcbulkheaded)
USB Host Controller Registers The HC head bulk register defines the local bus virtual address of the head ED on the bulk ED list. Table 14–12. HC Head Bulk Register (HcBulkHeadED) Reset Name Description Type Value 31–4 BHED Local bus virtual address of head ED on the bulk ED list This field represents bits 31:4 of the local bus virtual address of the head ED on the bulk ED list.
Page 967: Hc Head Done Register (Hcdonehead)
USB Host Controller Registers The HC head done register defines the local bus virtual address of the current head of the done TD queue. Table 14–14. HC Head Done Register (HcDoneHead) Reset Name Description Type Value 31–4 Local bus virtual address of the last TD that was added to 0x0000000 the done queue.
Page 968: Hc Frame Remaining Register (Hcfmremaining)
USB Host Controller Registers The HC frame remaining register reports the number of full speed bit times remaining in the current frame. Table 14–16. HC Frame Remaining Register (HcFmRemaining) Reset Name Description Type Value Frame remaining toggle This bit is loaded with the frame interval toggle bit every time the USB host controller loads the frame interval field into the frame remaining field.
Page 969: Hc Periodic Start Register (Hcperiodicstart)
USB Host Controller Registers The HC periodic start register defines the position within the USB frame where EDs on the periodic list have priority over EDs on the bulk and control lists. Table 14–18. HC Periodic Start Register (HcPeriodicStart) Reset Name Description Type...
Page 970: Hc Root Hub A Register (Hcrhdescriptora)
USB host controller driver is initialized. Because OMAP5910 does not provide a direct control from the USB host controller to switch VBUS on and off, this value must take into account any delays caused by other methods of controlling VBUS externally.
Page 971 The USB signal multiplexing mode and OMAP5910 top-level pin multiplexing features may place the OMAP5910 device in a mode where 0, 1, 2, or 3 of the USB host controller downstream ports are actually usable. This register reports three regardless of USB signal multiplexing mode and OMAP5910 top-level pin multiplexing mode.
Page 972: Hc Root Hub B Register (Hcrhdescriptorb)
PPCM bit 3 is the port power control mask for downstream port 3. PPCM bits 4 through 15 are reserved. OMAP5910 does not provide connections from the USB host controller to pins to provide external port power switching. Systems that implement port power switching must use other mechanisms to control port power.
Page 973: Hc Root Hub Status Register (Hcrhstatus)
USB Host Controller Registers The HC root hub status register reports the USB host controller root hub status. Table 14–22. HC Root Hub Status Register (HcRhStatus) Reset Name Description Type Value CRWE Clear remote wake-up enable Write of 0 has no effect. Write of 1 clears the device remote wake-up enable bit.
Page 974 (power switching mode = 1), a write of 1 turns off power to those ports whose corresponding PortPowerControlMask bit is 0. Because OMAP5910 does not provide signals from the USB host controller to external VBUS switching circuitry, this bit has no effect.
Page 975: Hc Port 1 Status And Control Register (Hcrhportstatus1)
The HC port 1 status and control register reports and controls the state of USB host port 1. HcRhPortStatus1 can provide status and control for the OMAP5910 USB port associated with the OMAP5910 integrated USB trans- ceiver according to the HMC_MODE value. See Section 14.5, USB Pin Multiplexing.
Page 976 This bit indicates, when read as 1, that the port 1 power is enabled. When read as 0, port 1 power is not enabled. The OMAP5910 does not provide signals from the USB host controller to control external port power, so, if required, USB host port power control signals must be controlled through other means.
Page 977 When read as 1, indicates a port 1 port overcurrent condition has occurred. When 0, no port 1 port overcurrent condition has occurred. OMAP5910 does not provide inputs for signaling external overcurrent indication to the USB host controller. Overcurrent monitoring, if required, must be handled through some other mechanism.
Page 978 USB Host Controller Registers Table 14–23. HC Port 1 Status and Control Register (HcRhPortStatus1) (Continued) Reset Name Description Type Value PES/SPE Port 1 port enable status/set port enable When read as 1, indicates that port 1 is enabled. When read as 0, this bit indicates that port 1 is not enabled.
Page 979: Hc Port 2 Status And Control Register (Hcrhportstatus2)
USB Host Controller Registers The HC port 2 status register reports and controls the state of USB host port 2. Depending on HMC_MODE value, HcRhPortStatus2 can provide status and control for the OMAP5910 USB Port 1 pins: CLK32K_OUT/USB1.SPEED BOOT/USB1.SUSP RST_HOST_OUT/USB1_SE0 MCBSP.CLK/USB1_TXEN...
Page 980 This bit indicates, when read as 1, that the port 2 power is enabled. When read as 0, port 2 power is not enabled. The OMAP5910 does not provide signals from the USB host controller to control external port power, so, if required, USB host port power control signals must be controlled through other means.
Page 981 When read as 1, indicates that a port 2 port overcurrent condition has occurred. When 0, no port 2 port overcurrent condition has occurred. The OMAP5910 does not provide inputs for signaling external overcurrent indication to the USB host controller. Overcurrent monitoring, if required, must be handled through some other mechanism.
Page 982 USB Host Controller Registers Table 14–24. HC Port 2 Status and Control Register (HcRhPortStatus2) (Continued) Reset Name Description Type Value PES/SPE Port 2 port enable status/set port enable When read as 1, indicates that port 2 is enabled. When read as 0, this bit indicates that port 2 is not enabled.
Page 983: Hc Port 3 Status And Control Register (Hcrhportstatus3)
USB Host Controller Registers The HC port 3 status and control register reports and controls the state of USB host port 3. Depending on HMC_MODE value, HcRhPortStatus2 can provide status and control for the OMAP5910 USB port 2 pins: MCSI2.CLK/USB2_SUSP UART2.RTS/USB2_SE0 MCSI2.DOUT/USB2.TXEN...
Page 984 This bit indicates, when read as 1, that the port 3 power is enabled. When read as 0, port 3 power is not enabled. The OMAP5910 does not provide signals from the USB host controller to control external port power, so, if required, USB host port power control signals must be controlled through other means.
Page 985 When read as 1, indicates that a port 3 port overcurrent condition has occurred. When 0, no port 3 port overcurrent condition has occurred. The OMAP5910 does not provide inputs for signaling external overcurrent indication to the USB host controller. Overcurrent monitoring, if required, must be handled through some other mechanism.
Page 986 USB Host Controller Registers Table 14–25. HC Port 3 Status and Control Register (HcRhPortStatus3) (Continued) Reset Name Description Type Value PES/SPE Port 3 port enable status/set port enable When read as 1, indicates that port 3 is enabled. When read as 0, this bit indicates that port 3 is not enabled.
Page 987: Host Ue Address Register (Hostueaddr)
USB Host Controller Registers The host UE address register reports the local bus virtual address of the last local bus access which caused an unrecoverable error (UE). This register has no meaning until an unrecoverable error has occurred. It also has no meaning if the USB host controller issues an unrecoverable error because the offset checking fault occurred while processing an isochronous TD.
Page 988: Host Ue Status Register (Hostuestatus)
USB Host Controller Registers The host UE status register reports the local bus cycle type for the last unre- coverable error that occurred. This register has no meaning until an unrecov- erable error has occurred. It also has no meaning if the USB host controller issues an unrecoverable error because the offset checking fault occurred while processing an isochronous TD.
Page 989: Host Time-Out Control Register (Hosttimeoutctrl)
This bit has no effect on MPU, DSP, or DMA controller accesses to local bus slave peripherals. The host revision register returns the revision number for the OMAP5910 USB host controller. This register is not defined by the OHCI specification.
Page 990: Usb Host Controller Registers
14.3.2 Endianism and USB Host Controller Registers The OMAP5910 USB host controller assumes that all MPU accesses to its reg- isters are 32-bit accesses. This restriction means that the host controller driver software may operate in either big-endian or little-endian without having to per- form endian conversion on USB host controller register accesses.
Page 991: Usb Host Controller Interrupt Sources
14.4 USB Host Controller Interrupt Sources 14.4.1 OHCI Interrupts The OMAP5910 USB host controller provides an interrupt output to the MPU level 2 interrupt handler on its IRQ_06 interrupt input. This is a level-sensitive interrupt signal, and the MPU level 2 interrupt handler IRQ_06 must be programmed as a level-sensitive input.
Page 992: Local Bus Mmu Interrupts
OHCI Root Hub Status Change The OHCI root hub status change interrupt is supported as described in the OHCI Specification for USB. The OMAP5910 does not provide a connection between the USB host controller and USB port overcurrent detection hard- ware, so the root hub status change interrupt does not occur due to a port over- current event.
Page 993: Usb Pin Multiplexing
USB Pin Multiplexing 14.5 USB Pin Multiplexing OMAP5910 USB signal multiplexing provides five main types of signaling: USB host and USB function with USB transceivers, USB host and USB func- tion without USB transceivers, and UART1. This section describes first gener-...
Page 994: Usb Function Controller Connectivity With Usb Transceivers
USB host controller or with USB transceivers that use TXD+ and TXD– signaling. Because OMAP5910 does not provide a pin that connects to the USB host controller port power control registers, some other mechanism must be used if VBUS switching is required.
Page 995: On-Board Transceiverless Connection Using Omap5910 Transceiverless Link Logic
USB function controller are removed. The transceiverless link logic signaling system is not suitable for use across a cable. It is intended only for use when the OMAP5910 device is used with an external USB integrated circuit which is on the same board.
Page 996: Omap5910 Usb Host Controller Connection—With And Without The Omap5910 Transceiverless Link Logic
OMAP5910 transceiverless link logic. Figure 14–6 shows OMAP5910 used as a USB function controller, with the top portion of the diagram showing a transceiver-based solution and the bottom portion showing a transceiverless solution using the OMAP5910 transceiverless link logic.
Page 997: Usb Signal Multiplexing Mode Diagrams
14.5.4 USB Signal Multiplexing Mode Diagrams The OMAP5910 USB signal multiplexing mechanisms provide a wide variety of options for bringing USB functionality to the OMAP5910 pins. These options are listed in Table 14–30 and are shown in Figure 14–7 through Figure 14–31.
Page 998: Usb Signal Multiplexing Modes
† CONF_MOD_USB_HOST_HMC_MODE_R values that select UART 1 bring UART1 CTS, RX, and TX signals to pins that can, in other CONF_MOD_USB_HOST_HMC_MODE_R values, be used for USB. ‡ CONF_MOD_USB_HOST_HMC_MODE_R 7 provides an internal signal path from six of the USB-related OMAP5910 input pins to six of the USB-related OMAP5910 output pins.
Page 999 † CONF_MOD_USB_HOST_HMC_MODE_R values that select UART 1 bring UART1 CTS, RX, and TX signals to pins that can, in other CONF_MOD_USB_HOST_HMC_MODE_R values, be used for USB. ‡ CONF_MOD_USB_HOST_HMC_MODE_R 7 provides an internal signal path from six of the USB-related OMAP5910 input pins to six of the USB-related OMAP5910 output pins.
Page 1000: Omap5910 With Conf_Mod_Usb_Host_Hmc_Mode_R Set To 0
USB Pin Multiplexing Figure 14–7. OMAP5910 With CONF_MOD_USB_HOST_HMC_MODE_R Set to 0 Level GPIO00/ USB.VBUS * translator USB host USB singal USB.PUEN controller multiplexing Host port 1 Transient USB0.DP USB0.DM suppressor transceiver Host port 2 CLK3 2K _OUT ** /USB1.SPEED Host port 3 MPU_BOOT** /USB1.SUSP...

Texas Instruments OMAP5910 Technical Reference Manual

2 MPU Subsystem

3 DSP Subsystem

4 Memory Interface Traffic Controller

5 System DMA Controller

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