Pin Control Register Configuration - Texas Instruments OMAP5910 Technical Reference Manual

7.10.1.10 Serial Port Control Register Configuration
7.10.1.11

Pin Control Register Configuration

Table 7–85. Pin Control Register Configuration
Bit Configuration Value
15–14 00b
13 0b
12 0b
11 1b
10 0b
9 1b
8 0b
7 0b
6 0b
5 0b
4 0b
3 0b
2 0b
1 0b
0 0b
Section 7.10.1.10 through Section 7.10.1.18 explain how to set up the McBSP
registers for TX master and RX slave mode with 16-bit transfers using DMA
support.
ARM_Write(0x0000) => SPCR1; set up SPCR1 as initial configuration.
This setup is not needed after reset.
ARM_Write(0x0000) => SPCR2; set up SPCR2 as initial configuration.
This setup is not needed after reset.
ARM_Write(0x0a00) => PCR; set up PCR per below configuration.
Description
Reserved
Set serial port mode for DX, FSX and CLKX pins
Set serial port mode for DR, FSR and CLKR pins
TX frame-synchronization signal driven by internal generator
RX frame-synchronization signal derived by external source
CLKX set output pin and driven by internal generator
CLKR set input pin and derived by external source
Sample rate generator input clock mode bit
CLKS pin status (no meaning in OMAP5910)
DX pin status
DR pin status
Set FSX polarity as active high
Set FSR polarity as active high
Set CLKX polarity as data driven on rising edge
Set CLKR polarity as data sampled on falling edge
MPU Public Peripherals
McBSP2
7-113