Lcd Top Address For Frame Buffer 1-Lower Bits Register; Lcd Top Address For Frame Buffer 1-Upper Bits Register - Texas Instruments OMAP5910 Technical Reference Manual

Table 5–25. DMA LCD Control Register (DMA_LCD_CTRL) (Continued)
Bit Name
0 FRAME_MODE
5.6.1.1 LCD Top Address for Frame Buffer 1 Registers (DMA_LCD_TOP_F1_L and
DMA_LCD_TOP_F1_U)
Table 5–26. LCD Top Address for Frame Buffer 1—Lower Bits Register
(DMA_LCD_TOP_F1_L)
Bit Name
15–1 LCD_TOP_F1_
L[15–1]
0 LCD_TOP_F1_
L[0]
Table 5–27. LCD Top Address for Frame Buffer 1—Upper Bits Register
(DMA_LCD_TOP_F1_U)
Bit Name
15–0 LCD_TOP_F1_
L[31–16]
Value Description
Kind of frame mode used for LCD transfer
0 One frame buffer; only registers for frame 1 are used.
1 Two frame buffers; LCD channel reads alternatively
top_frame_1 and top_frame_2
The LCD top address registers are two 16-bit registers that contain the start
address for the video RAM buffer 1. The 32-bit address is obtained by the
concatenation of the two 16-bit words as described here:
LCD_TOP_F1 = DMA_LCD_TOP_F1_U & DMA_LCD_TOP_F1_L.
Note:
LSB of the 32-bit word is equal to zero. Address of video buffer must always
be even.
Description
LCD top address for frame buffer 1 lower bits [15–1]
Address bit 0. Fixed at 0 since address must be even.
Description
LCD top address for frame buffer 1 upper bits [31–16]
Type
RW
Type
RW
R
Type
RW
System DMA Controller
Registers
Reset
Value
0
Reset
Value
Unde-
fined
0
Reset
Value
Unde-
fined
5-55