Frame Adjustment Reference Count Register (Farc); Frame Start Count Register (Fsc) - Texas Instruments OMAP5910 Technical Reference Manual

Dual-core
Hide thumbs Also See for OMAP5910:
Table of Contents

Advertisement

Table 7–147. Frame Adjustment Reference Count Register (FARC)
Bit
Name
15–0
FARC
Table 7–148. Frame Start Count Register (FSC)
Bit
Name
15–0
FS
The frame-adjustment counter register (FARC) is programmed with the
number of frame synchronization counts over which the frame start pulses are
counted. This is a 16-bit programmable fixed reference in the range of
0-65536. A value of zero disables the count operation.
Function
16-bit value in the range 0-65536: 0 = disable counting
The frame-start count register (FSC) is a 16-bit read-only register that contains
the number of frame-start rising edges that occur during the programmable
FARC period. The frame start counting can be in two modes. When the CNT
bit in the control and configuration register (CTRL) is set to one, the counting
is in continuous mode and this register is periodically updated (every time the
frame adjustment reference count is met) with the new count value. If CNT is
zero, the counting is in halt mode. The frame-start count register is updated
when the frame adjustment reference count is met, and the counting halts until
the software reads the FSC register.
A level-sensitive interrupt can be generated to indicate that the frame-start
counting is finished, and the FSC register is loaded with a new count value.
The interrupt is controlled by the INT_ENABLE bit in the control and configura-
tion register (CTRL). If this bit is set to one, an interrupt is generated when the
FSC register is updated. Since the interrupt is level-sensitive, the interrupt sig-
nal is kept low until the software reads the FSC register or the RUN bit in the
control register is set to zero. When the FSC is read or RUN bit in control regis-
ter is set to zero, the interrupt signal is reset to one. When in IN_ENABLE bit
is set to zero, no interrupt is generated. The interrupt can be enabled or
disabled for both continuous mode and halt mode.
Function
16-bit value
Frame Adjustment Counter
MPU Public Peripherals
Reset
Value
0
Reset
Value
0
7-203

Advertisement

Table of Contents
loading

Table of Contents