Image Data Register (Camdata); Clock Switching Procedures - Texas Instruments OMAP5910 Technical Reference Manual

Camera Interface
Table 7-9. Image Data Register (CAMDATA)
Bit Name
31-0 CAMDATA
Table 7-10. FIFO Peak Counter Register (PEAK_COUNTER)
Bit Name
31-7 RESERVED
6-0 PEAK_COUNTER
7.2.2

Clock Switching Procedures

7.2.2.1 CAM.EXCLK Switch Protocol
7.2.2.2 CAM.LCLK Switch Protocol
7-16
Function
Image data from FIFO
Function
Reserved
Maximum number of words written to FIFO
during the transfer since the last clear to zero
The CAM.EXCLK switch protocol is required for any change of the
CAM.EXCLK frequency value to first disable both 12-MHz clock source and
the DPLL clock source in clock control registers:
1) Disable MCLK and DPLL_CLK (MCLK_EN = 0, DPLL_EN = 0,
FOSCMOD = FOSCMOD).
2) Change CAM.EXCLK value (FOSCMOD = new FOSCMOD).
3) Enable MCLK and DPLL_CLK (MCLK_EN = 1, DPLL_EN = 1,
FOSCMOD = FOSCMOD).
Bit 3 of the clock control register (POLCLK) sets the polarity of CAM.LCLK. You
must disable CAM.LCLK before selecting the rising or the falling edge.
1) Disable CAM.LCLK (LCLK_EN = 0).
2) Set the new polarity (POLCLK = 1 or 0).
3) Enable CAM.LCLK (LCLK_EN = 1).
Reset
R/W
Value
R 0x0
Reset
R/W Value
R/W Unknown
R/W 0x0000000