Dma Controller Operational Events And Their Associated Bits And Interrupts; Interrupt Support - Texas Instruments OMAP5910 Reference Manual

7.2.15

Interrupt Support

Table 58. DMA Controller Operational Events and Their Associated Bits and Interrupts
Operational Event
Block transfer is complete
Last frame transfer has started
Frame transfer is complete
First half of current frame has been transferred
Synchronization event has been dropped
Timeout error has occurred
†
For a frame with an odd number of elements, the half-frame event occurs as soon as the number of elements transferred is
greater than the number that remains to be transferred. For example, for a frame of five elements, the half-frame event occurs
when the DMA controller has transferred three of the elements.
SPRU890A
The DMA controller can send an interrupt to the DSP core in response to the
operational events listed in Table 58. Each channel has interrupt enable (IE)
bits in the interrupt control register (DMACICR) and some corresponding
status bits in the status register (DMACSR). (DMACICR and DMACSR are
described in section 7.3.6). If one of the operational events in the table occurs,
the DMA controller checks the corresponding IE bit and acts accordingly:
If the IE bit is 1 (the interrupt is enabled), the DMA controller sets the
-
corresponding status bit and sends the associated interrupt request to the
DSP core. DMACSR is automatically cleared if your program reads the
register.
If the IE bit is 0, no interrupt is sent and the status bit is not affected.
-
DMACSR also has a SYNC bit that is used if you choose a synchronization
event for the channel. SYNC indicates when the selected synchronization
event has occurred (SYNC = 1) and when it has been serviced
(SYNC = 0). For more details about synchronization events, see section
7.2.12.
†
Interrupt
Enable Bit
Status Bit
BLOCKIE BLOCK
LASTIE LAST
FRAMEIE FRAME
HALFIE HALF
DROPIE DROP
TIMEOUTIE TIMEOUT
DSP Subsystem
DSP DMA
Associated
Interrupt
Channel interrupt
Channel interrupt
Channel interrupt
Channel interrupt
Channel interrupt
Bus-error interrupt
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