C55X Dsp Core Overview; Dsp Core Features - Texas Instruments OMAP5910 Reference Manual

2

C55x DSP Core Overview

2.1

DSP Core Features

SPRU890A
The DSP subsystem is based on the TMS320C55x DSP generation processor
core. This section is intended to give a mere overview of the C55x DSP core.
For detailed information, see the TMS320C55x DSP CPU Reference Guide
(SPRU371).
Features of the high-performance, low-power DSP core include:
Advanced multiple-bus architecture with one internal program memory
-
bus and five internal data buses (three dedicated to reads and two
dedicated to writes)
Unified program/data memory architecture
-
Dual 17-bit x 17-bit multipliers coupled to 40-bit dedicated adders for
-
non-pipelined single-cycle multiply accumulate (MAC) operations
Two address generators with eight auxiliary registers and two auxiliary
-
register arithmetic units
8M x 16 bits (16M bytes) of total addressable memory space
-
Single-instruction repeat or block repeat operations for program code
-
Conditional execution
-
Seven-stage pipeline for high instruction throughput
-
Instruction buffer unit that loads, parses, queues, and decodes
-
instructions to decouple the program fetch function from the pipeline
Program flow unit that coordinates program actions among multiple
-
parallel DSP core functional units
Address data flow unit that provides data address generation and includes
-
a 16-bit arithmetic unit capable of performing arithmetical, logical, shift,
and saturation operations
Data computation unit containing the primary computation units of the
-
DSP core, including a 40-bit arithmetic logic unit, two MAC units, and a
shifter
Software-programmable idle
-
low-power modes
Automatic power management
-
C55x DSP Core Overview
domains that provide configurable
DSP Subsystem 21