Mmu Tlb Entry Flush Register (Flush_Entry_Reg) - Texas Instruments OMAP5910 Reference Manual

DSP Memory Management Unit
6.5.14

MMU TLB Entry Flush Register (FLUSH_ENTRY_REG)

Figure 60. MMU TLB Entry Flush Register (FLUSH_ENTRY_REG)
31
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
Table 38. MMU TLB Entry Flush Register (FLUSH_ENTRY_REG) Field Descriptions
Bits Field
31−1 Reserved
0 FLUSH_ENTRY
116 DSP Subsystem
The TLB Entry Flush Register deletes individual entries from the TLB. When
the FLUSH_ENTRY bit is set, the preserved and valid bits of the entry pointed
to by the victim pointer are cleared.
Reserved
R-0
Value Description
These bits are not used.
TLB entry flush. Setting this bit flushes the entry pointed to by the
victim pointer.
0 The TLB entry flush is complete.
1 Flush the TLB entry pointed to by the victim pointer.
1 0
FLUSH_
ENTRY
RW-0
SPRU890A