Control Mode Register (Cmr) - Value At Reset Is 0Xfe4D - Texas Instruments OMAP5910 Technical Reference Manual

3.5.1 Control Mode Register (CMR)
Table 3–7. Control Mode Register (CMR) – Value at Reset is 0xFE4D
CMR
Designation
[15–0]
15–9 Time-out (6:0)
8–6 Wait state
(strobe2)
5–3 Wait state
(strobe1)
2 CPU priority
1 Bus error
0 Mode
The CMR indicates shared access mode/host-only mode (SAM/HOM) status
of the MPUI and bus error condition status for accesses to the TIPB bridge.
It also controls CPU priority versus the MPUI and DMA for accesses to
peripherals on the TIPB bridge.
Description
Strobe cycles
(0-127)
Strobe1 length
(low, medium, high
bits)
Strobe1 length
(low, medium, high
bits)
Priority modes
Application flag
error
SAM or HOM
-
Mode bit
This bit is a read-only indication of whether the MPUI is in host-only mode
(HOM) or in single-access mode (SAM). HOM and SAM are described in
Section 3.6, MPU Interface.
-
Bus error
This bit is set to 1 if the TIPB bridge generates a bus error (due to a time-out
condition or SAM/HOM change error), indicating that an error signal has
been sent to the DSP CPU, which can read this bit to identify the source of
the error condition. The bit is cleared upon read by the DSP CPU. This bit
cannot be read during HOM (always registers as zero during HOM).
-
CPU priority bit
When CPU_Priority = 1, the DSP subsystem CPU, MPUI, and DMA have
the following priority in arbitration of TIPB bridge accesses:
1) CPU
2) MPUI
Reset
CPU Access
Value
0x7F Read/Write
0 Read/Write
1 Read/Write
1 Read/Write
0 Read/Clear
1 (HOM) Read
TIPB Bridge
MPU Access
Read
Read
Read
Read
Read (0 in HOM)
Read
DSP Subsystem 3-29